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Publications of Author

1. Mark Hempstead, Gu-Yeon Wei, David Brooks
   Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations. [Citation Graph (0, 0)][DBLP]
   CASES, 2006, pp:368-378 [Conf]
   
2. Xuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Yue-Kai Huang, Paul R. Prucnal
   Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems. [Citation Graph (0, 0)][DBLP]
   HPCA, 2005, pp:120-131 [Conf]
   
3. Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu-Yeon Wei, David Brooks
   An Ultra Low Power System Architecture for Sensor Network Applications. [Citation Graph (0, 0)][DBLP]
   ISCA, 2005, pp:208-219 [Conf]
   
4. Yong-Cheol Bae, Gu-Yeon Wei
   A mixed PLL/DLL architecture for low jitter clock generation. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2004, pp:788-791 [Conf]
   
5. Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei, Un-Ku Moon
   Jitter in high-speed serial and parallel links. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2004, pp:425-428 [Conf]
   
6. Ruwan Ratnayake, Gu-Yeon Wei, Aleksandar Kavcic
   Pipelined parallel architecture for high throughput MAP detectors. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2004, pp:505-508 [Conf]
   
7. Gu-Yeon Wei, Mark Horowitz
   A low power switching power supply for self-clocked systems. [Citation Graph (0, 0)][DBLP]
   ISLPED, 1996, pp:313-317 [Conf]
   
8. Wai-Chi Fang, Sharon Kedar, Susan Owen, Gu-Yeon Wei, David Brooks, Jonathan Lees
   System-on-Chip Architecture Design for Intelligent Sensor Networks. [Citation Graph (0, 0)][DBLP]
   IIH-MSP, 2006, pp:579-582 [Conf]
   
9. Meeta S. Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, David M. Brooks
   Understanding voltage variations in chip multiprocessors using a distributed power-delivery network. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:624-629 [Conf]
   
10. 
    An accelerator-based wireless sensor network processor in 130nm CMOS. [Citation Graph (, )][DBLP]
    
    
11. 
    Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack. [Citation Graph (, )][DBLP]
    
    
12. 
    An event-guided approach to reducing voltage noise in processors. [Citation Graph (, )][DBLP]
    
    
13. 
    DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors. [Citation Graph (, )][DBLP]
    
    
14. 
    System level analysis of fast, per-core DVFS using on-chip switching regulators. [Citation Graph (, )][DBLP]
    
    
15. 
    Voltage emergency prediction: Using signatures to reduce operating margins. [Citation Graph (, )][DBLP]
    
    
16. 
    Evaluation of voltage interpolation to address process variations. [Citation Graph (, )][DBLP]
    
    
17. 
    Serial Sum-Product Architecture for Low-Density Parity-Check Codes. [Citation Graph (, )][DBLP]
    
    
18. 
    A review of actuation and power electronics options for flapping-wing robotic insects. [Citation Graph (, )][DBLP]
    
    
19. 
    Milligram-scale high-voltage power electronics for piezoelectric microrobots. [Citation Graph (, )][DBLP]
    
    
20. 
    ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency. [Citation Graph (, )][DBLP]
    
    
21. 
    Thread motion: fine-grained power management for multi-core systems. [Citation Graph (, )][DBLP]
    
    
22. 
    System design considerations for sensor network applications. [Citation Graph (, )][DBLP]
    
    
23. 
    Towards a software approach to mitigate voltage emergencies. [Citation Graph (, )][DBLP]
    
    
24. 
    Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies. [Citation Graph (, )][DBLP]
    
    
25. 
    Instruction-driven clock scheduling with glitch mitigation. [Citation Graph (, )][DBLP]
    
    
26. 
    Place and route considerations for voltage interpolated designs. [Citation Graph (, )][DBLP]
    
    
27. 
    Process Variation Tolerant 3T1D-Based Cache Architectures. [Citation Graph (, )][DBLP]
    
    
28. 
    Tribeca: design for PVT variations with local recovery and fine-grained adaptation. [Citation Graph (, )][DBLP]
    
    
29. 
    A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders. [Citation Graph (, )][DBLP]