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Dominique Borrione: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Diana Toma, Dominique Borrione, Ghiath Al Sammane
    Combining Several Paradigms for Circuit Validation and Verification. [Citation Graph (0, 0)][DBLP]
    CASSIS, 2004, pp:229-249 [Conf]
  2. David Déharbe, Dominique Borrione
    Semantics of a verification-oriented subset of VHDL. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:293-310 [Conf]
  3. Dominique Borrione, F. Vestman, H. Bouamama
    An approach to Verilog-VHDL interoperability for synchronous designs. [Citation Graph (0, 0)][DBLP]
    CHARME, 1997, pp:65-87 [Conf]
  4. Ghiath Al Sammane, Diana Toma, Julien Schmaltz, Pierre Ostier, Dominique Borrione
    Constrained Symbolic Simulation with Mathematica and ACL2. [Citation Graph (0, 0)][DBLP]
    CHARME, 2003, pp:150-157 [Conf]
  5. Ayman Wahba, Dominique Borrione
    Design error diagnosis in sequential circuits. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:171-188 [Conf]
  6. Joel Blasquez, Marten van Hulst, Andrea Fedeli, Jean-Luc Lambert, Dominique Borrione, Coby Hanoch, Pierre Bricaud
    Formal Verification Techniques: Industrial Status and Perspectives. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1050-1051 [Conf]
  7. Katell Morin-Allory, Dominique Borrione
    Proven correct monitors from PSL specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1246-1251 [Conf]
  8. Yann Oddos, Katell Morin-Allory, Dominique Borrione
    Prototyping Generators for On-line Test Vector Generation Based on PSL Properties. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:383-388 [Conf]
  9. Dominique Borrione, H. Bouamama, David Déharbe, C. Le Faou, Ayman Wahba
    HDL-Based Integration of Formal Methods and CAD Tools in the PREVAIL Environment. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:450-467 [Conf]
  10. Julien Schmaltz, Dominique Borrione
    A Functional Approach to the Formal Specification of Networks on Chip. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2004, pp:52-66 [Conf]
  11. Ghiath Al Sammane, Dominique Borrione, Remy Chevallier
    Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:260-263 [Conf]
  12. Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Sirianni
    An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. [Citation Graph (0, 0)][DBLP]
    HICSS, 2003, pp:279- [Conf]
  13. Dominique Borrione, Paolo Prinetto
    Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1989, pp:233-240 [Conf]
  14. Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Frederick J. Hill, Patrick Skelly
    An Overview of CONLAN: A Formal Construction Method for Hardware Description Language. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1980, pp:199-204 [Conf]
  15. Raimund Ubar, Dominique Borrione
    Design Error Diagnosis in Digital Circuits without Error Model. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:281-292 [Conf]
  16. S. Reda, Ayman M. Wahba, Ashraf M. Salem, Dominique Borrione, M. Ghonaimy
    On the use of don't cares during symbolic reachability analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:121-124 [Conf]
  17. Jorgiano Vidal, David Déharbe, Dominique Borrione
    Improving Static Ordering of BDDs for Reachability Analysis. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:73-77 [Conf]
  18. Emil Dumitrescu, Dominique Borrione
    Symbolic Simulation as a Simplifying Strategy for SoC Verification. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:378-383 [Conf]
  19. Katell Morin-Allory, Laurent Fesquet, Dominique Borrione
    Asynchronous Assertion Monitors for multi-Clock Domain System Verification. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2006, pp:98-102 [Conf]
  20. Ghiath Al Sammane, Julien Schmaltz, Diana Toma, Pierre Ostier, Dominique Borrione
    TheoSim: combining symbolic simulation and theorem proving for hardware verification. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:60-65 [Conf]
  21. Julien Schmaltz, Dominique Borrione
    A Generic Network on Chip Model. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 2005, pp:310-325 [Conf]
  22. Diana Toma, Dominique Borrione
    Formal Verification of a SHA-1 Circuit Core Using ACL2. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 2005, pp:326-341 [Conf]
  23. Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Sirianni
    Validation of asynchronous circuit specifications using IF/CADP. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:86-91 [Conf]
  24. Julien Schmaltz, Dominique Borrione
    Towards a formal theory of on chip communications in the ACL2 logic. [Citation Graph (0, 0)][DBLP]
    ACL2, 2006, pp:47-56 [Conf]
  25. Dominique Borrione, Robert Piloty, Dwight D. Hill, Karl J. Lieberherr, Philip Moorby
    Three Decades of HDLs: Part II, Conlan Through Verilog. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:3, pp:54-63 [Journal]
  26. Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem
    Formal Verification of VHDL Descriptions in the Prevail Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:2, pp:42-56 [Journal]
  27. Dominique Borrione, Ashraf M. Salem
    Denotational Semantics of a Synchronous VHDL Subset. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1995, v:7, n:1/2, pp:53-71 [Journal]
  28. Vanderlei Moraes Rodrigues, Dominique Borrione, Philippe Georgelin
    Using the ACL2 Theorem Prover to Reason about VHDL Components. [Citation Graph (0, 0)][DBLP]
    RITA, 2000, v:7, n:1, pp:129-148 [Journal]
  29. Yann Oddos, Katell Morin-Allory, Dominique Borrione
    On-Line Test Vector Generation from Temporal Constraints Written in PSL. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:397-402 [Conf]
  30. Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz
    A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:127-136 [Conf]
  31. Dominique Borrione, Julia Dushina, Laurence V. Pierre
    A compositional model for the functional verification of high-level synthesis results. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:526-530 [Journal]

  32. CONLAN: a formal construction method for hardware description languages: language derivation. [Citation Graph (, )][DBLP]


  33. CONLAN: a formal construction method for hardware description languages: basic principles. [Citation Graph (, )][DBLP]


  34. CONLAN: a formal construction method for hardware description languages: language application. [Citation Graph (, )][DBLP]


  35. Formalizing On Chip Communications in a Functional Style. [Citation Graph (, )][DBLP]


  36. Connection error location and correction in combinational circuits. [Citation Graph (, )][DBLP]


  37. High-level symbolic simulation for automatic model extraction. [Citation Graph (, )][DBLP]


  38. A process algebra interpretation of a verification oriented overlanguage of VHDL. [Citation Graph (, )][DBLP]


  39. MYGEN: automata-based on-line test generator for assertion-based verification. [Citation Graph (, )][DBLP]


  40. Assertion-Based Design with Horus. [Citation Graph (, )][DBLP]


  41. Executable formal specification and validation of NoC communication infrastructures. [Citation Graph (, )][DBLP]


  42. Asynchronous online-monitoring of logical and temporal assertions. [Citation Graph (, )][DBLP]


  43. On-line Monitoring of Properties Built on Regular Expressions. [Citation Graph (, )][DBLP]


  44. Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications. [Citation Graph (, )][DBLP]


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