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Doug Burger: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jaehyuk Huh, Doug Burger, Stephen W. Keckler
    Exploring the Design Space of Future CMPs. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:199-210 [Conf]
  2. Ramadass Nagarajan, Sundeep K. Kushwaha, Doug Burger, Kathryn S. McKinley, Calvin Lin, Stephen W. Keckler
    Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:74-84 [Conf]
  3. Doug Burger
    Designing Ultra-large Instruction Issue Windows. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:14-20 [Conf]
  4. Jaehyuk Huh, Jichuan Chang, Doug Burger, Gurindar S. Sohi
    Coherence decoupling: making use of incoherence. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:97-106 [Conf]
  5. Changkyu Kim, Doug Burger, Stephen W. Keckler
    An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:211-222 [Conf]
  6. Rajagopalan Desikan, Simha Sethumadhavan, Doug Burger, Stephen W. Keckler
    Scalable selective re-execution for EDGE architectures. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:120-132 [Conf]
  7. Katherine E. Coons, Xia Chen, Doug Burger, Kathryn S. McKinley, Sundeep K. Kushwaha
    A spatial path scheduling algorithm for EDGE architectures. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:129-140 [Conf]
  8. Aaron Smith, Jon Gibson, Bertrand A. Maher, Nicholas Nethercote, Bill Yoder, Doug Burger, Kathryn S. McKinley, James H. Burrill
    Compiling for EDGE Architectures. [Citation Graph (0, 0)][DBLP]
    CGO, 2006, pp:185-195 [Conf]
  9. Doug Burger
    Architectural versus physical solutions for on-chip communication challenges. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:74- [Conf]
  10. Premkishore Shivakumar, Michael Kistler, Stephen W. Keckler, Doug Burger, Lorenzo Alvisi
    Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic. [Citation Graph (0, 0)][DBLP]
    DSN, 2002, pp:389-398 [Conf]
  11. Wi-Fen Lin, Steven K. Reinhardt, Doug Burger
    Reducing DRAM Latencies with an Integrated Memory Hierarchy Design. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:301-312 [Conf]
  12. Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger
    Static Energy Reduction Techniques for Microprocessor Caches. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:276-283 [Conf]
  13. Wei-Fen Lin, Steven K. Reinhardt, Doug Burger, Thomas R. Puzak
    Filtering Superfluous Prefetches Using Density Vectors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:124-132 [Conf]
  14. Karthikeyan Sankaralingam, Vincent Ajay Singh, Stephen W. Keckler, Doug Burger
    Routed Inter-ALU Networks for ILP Scalability and Performance. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:170-0 [Conf]
  15. Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger
    Exploiting Microarchitectural Redundancy For Defect Tolerance. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:481-488 [Conf]
  16. Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger, Stephen W. Keckler
    A NUCA substrate for flexible CMP cache sharing. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:31-40 [Conf]
  17. Alain Kägi, Nagi Aboulenein, Doug Burger, James R. Goodman
    Techniques for Reducing Overheads of Shared-Memory Multiprocessing. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1995, pp:11-20 [Conf]
  18. Doug Burger, David A. Wood
    Accuracy vs. performance in parallel simulation of interconnection networks. [Citation Graph (0, 0)][DBLP]
    IPPS, 1995, pp:22-31 [Conf]
  19. Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, Doug Burger
    Clock rate versus IPC: the end of the road for conventional microarchitectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:248-259 [Conf]
  20. Doug Burger, James R. Goodman, Alain Kägi
    Memory Bandwidth Limitations of Future Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:78-89 [Conf]
  21. Doug Burger, Stefanos Kaxiras, James R. Goodman
    DataScalar Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:338-349 [Conf]
  22. M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas
    The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:14-24 [Conf]
  23. Alain Kägi, Doug Burger, James R. Goodman
    Efficient Synchronization: Let Them Eat QOLB. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:170-180 [Conf]
  24. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
    Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:422-433 [Conf]
  25. Zhenlin Wang, Doug Burger, Steven K. Reinhardt, Kathryn S. McKinley, Charles C. Weems
    Guided Region Prefetching: A Cooperative Hardware/Software Approach. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:388-398 [Conf]
  26. Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger
    Microprocessor pipeline energy analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:282-287 [Conf]
  27. Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler
    A design space evaluation of grid processor architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:40-51 [Conf]
  28. Karthikeyan Sankaralingam, Stephen W. Keckler, William R. Mark, Doug Burger
    Universal Mechanisms for Data-Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:303-314 [Conf]
  29. Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
    Scalable Hardware Memory Disambiguation for High ILP Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:399-410 [Conf]
  30. Bertrand A. Maher, Aaron Smith, Doug Burger, Kathryn S. McKinley
    Merging Head and Tail Duplication for Convergent Hyperblock Formation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:65-76 [Conf]
  31. Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley
    Dataflow Predication. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:89-102 [Conf]
  32. Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger
    Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:480-491 [Conf]
  33. Doug Burger, Rahmat S. Hyder, Barton P. Miller, David A. Wood
    Paging tradeoffs in distributed-shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    SC, 1994, pp:590-599 [Conf]
  34. Sarita V. Adve, Doug Burger, Rudolf Eigenmann, Alasdair Rawsthorne, Michael D. Smith, Catherine H. Gebotys, Mahmut T. Kandemir, David J. Lilja, Alok N. Choudhary, Jesse Zhixi Fang, Pen-Chung Yew
    Changing Interaction of Compiler and Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:51-58 [Journal]
  35. Doug Burger, James R. Goodman
    Billion-Transistor Architectures: There and Back Again. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:3, pp:22-28 [Journal]
  36. Doug Burger, James R. Goodman
    Billion-Transistor Architectures - Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:9, pp:46-49 [Journal]
  37. Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Michael Dahlin, Lizy Kurian John, Calvin Lin, Charles R. Moore, James H. Burrill, Robert G. McDonald, William Yode
    Scaling to the End of Silicon with EDGE Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:7, pp:44-55 [Journal]
  38. Doug Burger
    Memory Systems. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1996, v:28, n:1, pp:63-65 [Journal]
  39. Jaehyuk Huh, Doug Burger, Jichuan Chang, Gurindar S. Sohi
    Speculative Incoherent Cache Protocols. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:104-109 [Journal]
  40. Changkyu Kim, Doug Burger, Stephen W. Keckler
    Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:99-107 [Journal]
  41. Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
    Scalable Hardware Memory Disambiguation for High-ILP Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:118-127 [Journal]
  42. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
    Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:46-51 [Journal]
  43. Rajagopalan Desikan, Doug Burger, Stephen W. Keckler, Llorenc Cruz, Fernando Latorre, Antonio González, Mateo Valero
    Errata on "Measuring Experimental Error in Microprocessor Simulation". [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2002, v:30, n:1, pp:2-4 [Journal]
  44. Doug Burger, Todd M. Austin, Stephen W. Keckler
    Recent extensions to the SimpleScalar tool suite. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS Performance Evaluation Review, 2004, v:31, n:4, pp:4-7 [Journal]
  45. Doug Burger, Anand Sivasubramaniam
    Tools for computer architecture research. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS Performance Evaluation Review, 2004, v:31, n:4, pp:2-3 [Journal]
  46. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore
    TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:1, pp:62-93 [Journal]
  47. Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
    Designing a Modern Memory Hierarchy with Hardware Prefetching. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1202-1218 [Journal]
  48. Deependra Talla, Lizy Kurian John, Doug Burger
    Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:8, pp:1015-1031 [Journal]
  49. Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler
    Late-binding: enabling unordered load-store queues. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:347-357 [Conf]
  50. Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger
    Implementation and Evaluation of a Dynamically Routed Processor Operand Network. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:7-17 [Conf]
  51. Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger
    On-Chip Interconnection Networks of the TRIPS Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:41-50 [Journal]
  52. Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger, Stephen W. Keckler
    A NUCA Substrate for Flexible CMP Cache Sharing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:8, pp:1028-1040 [Journal]
  53. Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger
    Static energy reduction techniques for microprocessor caches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:303-313 [Journal]

  54. Multitasking workload scheduling on flexible-core chip multiprocessors. [Citation Graph (, )][DBLP]


  55. Feature selection and policy optimization for distributed instruction placement using reinforcement learning. [Citation Graph (, )][DBLP]


  56. Evolving Compiler Heuristics to Manage Communication and Contention. [Citation Graph (, )][DBLP]


  57. An evaluation of the TRIPS computer system. [Citation Graph (, )][DBLP]


  58. Dynamically replicated memory: building reliable systems from nanoscale resistive memories. [Citation Graph (, )][DBLP]


  59. Design and Implementation of the TRIPS Primary Memory System. [Citation Graph (, )][DBLP]


  60. Implementation and Evaluation of On-Chip Network Architectures. [Citation Graph (, )][DBLP]


  61. Counting Dependence Predictors. [Citation Graph (, )][DBLP]


  62. Architecting phase change memory as a scalable dram alternative. [Citation Graph (, )][DBLP]


  63. Use ECP, not ECC, for hard failures in resistive memories. [Citation Graph (, )][DBLP]


  64. End-to-end validation of architectural power models. [Citation Graph (, )][DBLP]


  65. Critical path analysis of the TRIPS architecture. [Citation Graph (, )][DBLP]


  66. Analysis of the TRIPS prototype block predictor. [Citation Graph (, )][DBLP]


  67. Register Bank Assignment for Spatially Partitioned Processors. [Citation Graph (, )][DBLP]


  68. Composable Lightweight Processors. [Citation Graph (, )][DBLP]


  69. Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency. [Citation Graph (, )][DBLP]


  70. Strategies for mapping dataflow blocks to distributed hardware. [Citation Graph (, )][DBLP]


  71. Low-power, high-performance analog neural branch prediction. [Citation Graph (, )][DBLP]


  72. High performance dense linear algebra on a spatially distributed processor. [Citation Graph (, )][DBLP]


  73. Better I/O through byte-addressable, persistent memory. [Citation Graph (, )][DBLP]


  74. Phase change memory architecture and the quest for scalability. [Citation Graph (, )][DBLP]


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