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Byoungro So: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alexandre E. Eichenberger, Kathryn M. O'Brien, Kevin O'Brien, Peng Wu, Tong Chen, Peter H. Oden, Daniel A. Prener, Janice C. Shepherd, Byoungro So, Zehra Sura, Amy Wang, Tao Zhang, Peng Zhao, Michael Gschwind
    Optimizing Compiler for the CELL Processor. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:161-172 [Conf]
  2. Byoungro So, Mary W. Hall
    Increasing the Applicability of Scalar Replacement. [Citation Graph (0, 0)][DBLP]
    CC, 2004, pp:185-201 [Conf]
  3. Byoungro So, Mary W. Hall, Heidi E. Ziegler
    Custom Data Layout for Memory Parallelism. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:291-302 [Conf]
  4. Byoungro So, Pedro C. Diniz, Mary W. Hall
    Using estimates from behavioral synthesis tools in compiler-directed design space exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:514-519 [Conf]
  5. Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro C. Diniz
    Coarse-Grain Pipelining on Multiple FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:77-0 [Conf]
  6. Byoungro So, Sungdo Moon, Mary W. Hall
    Measuring the Effectiveness of Automatic Parallelization in SUIF. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:212-219 [Conf]
  7. Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoungro So, Heidi E. Ziegler
    Bridging the Gap between Compilation and Synthesis in the DEFACTO System. [Citation Graph (0, 0)][DBLP]
    LCPC, 2001, pp:52-70 [Conf]
  8. Heidi E. Ziegler, Mary W. Hall, Byoungro So
    Search Space Properties for Mapping Coarse-Grain Pipelined FPGA Applications. [Citation Graph (0, 0)][DBLP]
    LCPC, 2003, pp:1-16 [Conf]
  9. Sungdo Moon, Byoungro So, Mary W. Hall, Brian R. Murphy
    A Case for Combining Compile-Time and Run-Time Parallelization. [Citation Graph (0, 0)][DBLP]
    LCR, 1998, pp:91-106 [Conf]
  10. Byoungro So, Mary W. Hall, Pedro C. Diniz
    A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-based Systems. [Citation Graph (0, 0)][DBLP]
    PLDI, 2002, pp:165-176 [Conf]
  11. Alexandre E. Eichenberger, Kevin O'Brien, Kathryn M. O'Brien, Peng Wu, Tong Chen, Peter H. Oden, Daniel A. Prener, Janice C. Shepherd, Byoungro So, Zehra Sura, Amy Wang, Tao Zhang, Peng Zhao, Michael Gschwind, Roch Archambault, Yaoqing Gao, Roland Koo
    Using advanced compiler technology to exploit the performance of the Cell Broadband EngineTM architecture. [Citation Graph (0, 0)][DBLP]
    IBM Systems Journal, 2006, v:45, n:1, pp:59-84 [Journal]
  12. Sungdo Moon, Byoungro So, Mary W. Hall
    Combining compile-time and run-time parallelization[1]This work has been supported by DARPA Contract DABT63-95-C-0118 and NSF Contract ACI-9721368. [Citation Graph (0, 0)][DBLP]
    Scientific Programming, 1999, v:7, n:3-4, pp:247-260 [Journal]
  13. Sungdo Moon, Byoungro So, Mary W. Hall
    Evaluating Automatic Parallelization in SUIF. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2000, v:11, n:1, pp:36-49 [Journal]
  14. Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoungro So, Heidi E. Ziegler
    Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:51-62 [Journal]

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