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Publications of Author

1. Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott
   Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2002, pp:141-0 [Conf]
   
2. Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook
   A circuit level implementation of an adaptive issue queue for power-aware microprocessors. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:73-78 [Conf]
   
3. Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler
   Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. [Citation Graph (0, 0)][DBLP]
   HPCA, 2005, pp:238-242 [Conf]
   
4. Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi
   Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2001, pp:289-300 [Conf]
   
5. Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose
   Energy Efficient Co-Adaptive Instruction Fetch and Issue. [Citation Graph (0, 0)][DBLP]
   ISCA, 2003, pp:147-156 [Conf]
   
6. Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster
   Tradeoffs in power-efficient issue queue design. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2002, pp:184-189 [Conf]
   
7. Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose
   Microarchitectural techniques for power gating of execution units. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2004, pp:32-37 [Conf]
   
8. Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
   Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. [Citation Graph (0, 0)][DBLP]
   MICRO, 2000, pp:245-257 [Conf]
   
9. Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, Margaret Martonosi
   An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. [Citation Graph (0, 0)][DBLP]
   MICRO, 2006, pp:347-358 [Conf]
   
10. Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, Alper Buyuktosunoglu
    Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches. [Citation Graph (0, 0)][DBLP]
    PACS, 2003, pp:180-195 [Conf]
    
11. Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas
    Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. [Citation Graph (0, 0)][DBLP]
    PACS, 2002, pp:1-17 [Conf]
    
12. Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi
    An Adaptive Issue Queue for Reduced Power at High Performance. [Citation Graph (0, 0)][DBLP]
    PACS, 2000, pp:25-39 [Conf]
    
13. David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster
    Dynamically Tuning Processor Resources with Adaptive Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:12, pp:49-58 [Journal]
    
14. David Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook
    Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2000, v:20, n:6, pp:26-44 [Journal]
    
15. Canturk Isci, Alper Buyuktosunoglu, Margaret Martonosi
    Long-Term Workload Phases: Duration Predictions and Applications to DVFS. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:5, pp:39-51 [Journal]
    
16. Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
    A Dynamically Tunable Memory Hierarchy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:10, pp:1243-1258 [Journal]
    
17. 
    ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs. [Citation Graph (, )][DBLP]
    
    
18. 
    Exploring power management in multi-core systems. [Citation Graph (, )][DBLP]
    
    
19. 
    Performance modeling for early analysis of multi-core systems. [Citation Graph (, )][DBLP]
    
    
20. 
    Power-efficient, reliable microprocessor architectures: modeling and design methods. [Citation Graph (, )][DBLP]
    
    
21. 
    Software-Controlled Priority Characterization of POWER5 Processor. [Citation Graph (, )][DBLP]
    
    
22. 
    Evaluating design tradeoffs in on-chip power management for CMPs. [Citation Graph (, )][DBLP]
    
    
23. 
    Dynamic power gating with quality guarantees. [Citation Graph (, )][DBLP]
    
    
24. 
    A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity. [Citation Graph (, )][DBLP]
    
    
25. 
    Program behavior prediction using a statistical metric model. [Citation Graph (, )][DBLP]