Scalable and reliable communication for hardware transactional memory. [Citation Graph (, )][DBLP]
Micro-pages: increasing DRAM efficiency with locality-aware data placement. [Citation Graph (, )][DBLP]
Non-uniform power access in large caches with low-swing wires. [Citation Graph (, )][DBLP]
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches. [Citation Graph (, )][DBLP]
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. [Citation Graph (, )][DBLP]
Rethinking DRAM design and organization for energy-constrained multi-cores. [Citation Graph (, )][DBLP]
Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. [Citation Graph (, )][DBLP]
Hardware prediction of OS run-length for fine-grained resource customization. [Citation Graph (, )][DBLP]
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. [Citation Graph (, )][DBLP]
Leveraging 3D Technology for Improved Reliability. [Citation Graph (, )][DBLP]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP