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Rajeev Balasubramonian: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott
    Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:141-0 [Conf]
  2. Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy
    Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:28-39 [Conf]
  3. Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott
    Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:29-42 [Conf]
  4. Rajeev Balasubramonian
    Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures. [Citation Graph (0, 0)][DBLP]
    ICS, 2004, pp:326-335 [Conf]
  5. Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
    Dynamically allocating processor resources between nearby and distant ILP. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:26-37 [Conf]
  6. Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
    Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:275-286 [Conf]
  7. Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter
    Interconnect-Aware Coherence Protocols for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:339-351 [Conf]
  8. Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
    Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:245-257 [Conf]
  9. Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
    Reducing the complexity of the register file in dynamic superscalar processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:237-248 [Conf]
  10. Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, Alper Buyuktosunoglu
    Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches. [Citation Graph (0, 0)][DBLP]
    PACS, 2003, pp:180-195 [Conf]
  11. David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster
    Dynamically Tuning Processor Resources with Adaptive Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:12, pp:49-58 [Journal]
  12. Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
    A Dynamically Tunable Memory Hierarchy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:10, pp:1243-1258 [Journal]
  13. Naveen Muralimanohar, Rajeev Balasubramonian
    Interconnect design considerations for large NUCA caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:369-380 [Conf]
  14. Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter
    Leveraging Wire Properties at the Microarchitecture Level. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:6, pp:40-52 [Journal]
  15. Niti Madan, Rajeev Balasubramonian
    Power Efficient Approaches to Redundant Multithreading. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:8, pp:1066-1079 [Journal]

  16. Scalable and reliable communication for hardware transactional memory. [Citation Graph (, )][DBLP]


  17. Micro-pages: increasing DRAM efficiency with locality-aware data placement. [Citation Graph (, )][DBLP]


  18. Non-uniform power access in large caches with low-swing wires. [Citation Graph (, )][DBLP]


  19. Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches. [Citation Graph (, )][DBLP]


  20. Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. [Citation Graph (, )][DBLP]


  21. Rethinking DRAM design and organization for energy-constrained multi-cores. [Citation Graph (, )][DBLP]


  22. Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. [Citation Graph (, )][DBLP]


  23. Hardware prediction of OS run-length for fine-grained resource customization. [Citation Graph (, )][DBLP]


  24. Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. [Citation Graph (, )][DBLP]


  25. Leveraging 3D Technology for Improved Reliability. [Citation Graph (, )][DBLP]


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