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Yan Solihin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Seongbeom Kim, Dhruba Chandra, Yan Solihin
    Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:111-122 [Conf]
  2. Brian Rogers, Milos Prvulovic, Yan Solihin
    Efficient data protection for distributed shared memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:84-94 [Conf]
  3. Mazen Kharbutli, Xiaowei Jiang, Yan Solihin, Guru Venkataramani, Milos Prvulovic
    Comprehensively and efficiently protecting the heap. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:207-218 [Conf]
  4. Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihin
    Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:340-351 [Conf]
  5. Mazen Kharbutli, Keith Irwin, Yan Solihin, Jaejin Lee
    Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:288-299 [Conf]
  6. Jaejin Lee, Yan Solihin, Josep Torrellas
    Automatically Mapping Code on an Intelligent Memory Architecture. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:121-0 [Conf]
  7. Mazen Kharbutli, Yan Solihin
    Counter-Based Cache Replacement Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:61-68 [Conf]
  8. Yan Solihin, Kirk W. Cameron, Yong Luo, Dominique Lavenier, Maya Gokhale
    Mutable Functional Units and Their Applications on Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:234-239 [Conf]
  9. Yan Solihin, Graham Leedham
    Mathematical properties of the native integral ratio handwriting and text extraction technique. [Citation Graph (0, 0)][DBLP]
    ICDAR, 1997, pp:1102-0 [Conf]
  10. Yan Solihin, Jaejin Lee, Josep Torrellas
    Adaptively Mapping Code in an Intelligent Memory Architecture. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:71-84 [Conf]
  11. Yan Solihin, Fei Guo, Seongbeom Kim
    Predicting Cache Space Contention in Utility Computing Servers. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  12. Changhee Jung, Daeseob Lim, Jaejin Lee, Yan Solihin
    Helper thread prefetching for loosely-coupled multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  13. Yan Solihin, Josep Torrellas, Jaejin Lee
    Using a User-Level Memory Thread for Correlation Prefetching. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:171-182 [Conf]
  14. Chenyu Yan, Daniel Englender, Milos Prvulovic, Brian Rogers, Yan Solihin
    Improving Cost, Performance, and Security of Memory Encryption and Authentication. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:179-190 [Conf]
  15. Fei Guo, Yan Solihin
    An analytical model for cache replacement policy performance. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS/Performance, 2006, pp:228-239 [Conf]
  16. Rithin Shetty, Mazen Kharbutli, Yan Solihin, Milos Prvulovic
    HeapMon: A helper-thread approach to programmable, automatic, and low-overhead memory bug detection. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2006, v:50, n:2-3, pp:261-276 [Journal]
  17. Yan Solihin, C. G. Leedham
    Integral Ratio: A New Class of Global Thresholding Techniques for Handwriting Images. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1999, v:21, n:8, pp:761-768 [Journal]
  18. Brian Rogers, Yan Solihin, Milos Prvulovic
    Memory predecryption: hiding the latency overhead of memory encryption. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:1, pp:27-33 [Journal]
  19. Mazen Kharbutli, Yan Solihin, Jaejin Lee
    Eliminating Conflict Misses Using Prime Number-Based Cache Indexing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:5, pp:573-586 [Journal]
  20. Yan Solihin, Jaejin Lee, Josep Torrellas
    Automatic Code Mapping on an Intelligent Memory Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1248-1266 [Journal]
  21. Yan Solihin, Jaejin Lee, Josep Torrellas
    Correlation Prefetching with a User-Level Memory Thread. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:6, pp:563-580 [Journal]
  22. Yan Solihin, Fei Guo, Seongbeom Kim, Fang Liu
    Supporting Quality of Service in High-Performance Servers. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  23. Ravi R. Iyer, Li Zhao, Fei Guo, Ramesh Illikkal, Srihari Makineni, Donald Newell, Yan Solihin, Lisa R. Hsu, Steven K. Reinhardt
    QoS policies and architecture for cache/memory in CMP platforms. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2007, pp:25-36 [Conf]

  24. Architecture Support for Improving Bulk Memory Copying and Initialization Performance. [Citation Graph (, )][DBLP]


  25. Characterizing and modeling the behavior of context switch misses. [Citation Graph (, )][DBLP]


  26. MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging. [Citation Graph (, )][DBLP]


  27. FlexiTaint: A programmable accelerator for dynamic taint propagation. [Citation Graph (, )][DBLP]


  28. Single-level integrity and confidentiality protection for distributed shared memory multiprocessors. [Citation Graph (, )][DBLP]


  29. Scaling the bandwidth wall: challenges in and avenues for CMP scaling. [Citation Graph (, )][DBLP]


  30. Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance. [Citation Graph (, )][DBLP]


  31. Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly. [Citation Graph (, )][DBLP]


  32. A Framework for Providing Quality of Service in Chip Multi-Processors. [Citation Graph (, )][DBLP]


  33. Animations of important concepts in parallel computer architecture. [Citation Graph (, )][DBLP]


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