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Raymond Hoare: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Soohong P. Kim, Raymond Hoare, Henry G. Dietz
    VLIW Across Multiple Superscalar Processors on a Single Chip. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1997, pp:166-0 [Conf]
  2. Joshua M. Lucas, Raymond Hoare, Alex K. Jones
    Optimizing Technology Mapping for FPGAs Using CAMs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:293-294 [Conf]
  3. Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster
    An FPGA-based VLIW processor with custom hardware execution. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:107-117 [Conf]
  4. Henry G. Dietz, Raymond Hoare, Timothy Mattox
    A Fine-Grain Parallel Architecture Based on Barrier Synchronization. [Citation Graph (0, 0)][DBLP]
    ICPP, Vol. 1, 1996, pp:247-250 [Conf]
  5. Raymond Hoare
    ClusterNet: An Object-Oriented Cluster Network. [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:28-38 [Conf]
  6. Raymond Hoare, Henry G. Dietz
    A Case for Aggregate Networks. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:162-166 [Conf]
  7. Raymond Hoare, Shen Chih Tung, Katrina Werger
    An 88-Way Multiprocessor within an FPGA with Customizable Instructions. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  8. Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster
    Extracting Speedup From C-Code With Poor Instruction-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  9. David Reed, Raymond Hoare
    An SoC Solution for Massive Parallel Processing. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  10. Raymond Hoare, Shen Chih Tung
    Combining Mentor Graphics? HDL Designer FPGA Flow with a Reconfigurable System on a Programmable Chip, Educational Opportunity or Insanity? [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:128-130 [Conf]
  11. Alex K. Jones, Raymond Hoare, Dara Kusic, Gayatri Mehta, Joshua Fazekas, John Foster
    Reducing power while increasing performance with supercisc. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:3, pp:658-686 [Journal]
  12. Joshua M. Lucas, Raymond Hoare, Ivan S. Kourtev, Alex K. Jones
    Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:7, pp:445-456 [Journal]
  13. Alex K. Jones, Raymond Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle
    An automated, FPGA-based reconfigurable, low-power RFID tag. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:2, pp:116-134 [Journal]

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