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Alexander V. Veidenbaum :
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Sunil Kim , Alexander V. Veidenbaum The Effect of Limited Network Bandwidth and its Utilization by Latency Hiding Techniques in Large-Scale Shared Memory Systems. [Citation Graph (0, 0)][DBLP ] IEEE PACT, 1997, pp:40-51 [Conf ] Juan L. Aragón , Alexander V. Veidenbaum Energy-Effective Instruction Fetch Unit for Wide Issue Processors. [Citation Graph (0, 0)][DBLP ] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:15-27 [Conf ] José L. Ayala , Marisa Luisa López-Vallejo , Alexander V. Veidenbaum , Carlos A. Lopez Energy Aware Register File Implementation through Instruction Predecode. [Citation Graph (0, 0)][DBLP ] ASAP, 2003, pp:86-96 [Conf ] Arun Kejariwal , Alexander V. Veidenbaum , Alexandru Nicolau , Milind Girkarmark , Xinmin Tian , Hideki Saito Challenges in exploitation of loop parallelism in embedded applications. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2006, pp:173-180 [Conf ] Ana Azevedo , Ilya Issenin , Radu Cornea , Rajesh Gupta , Nikil D. Dutt , Alexander V. Veidenbaum , Alexandru Nicolau Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:168-175 [Conf ] Juan L. Aragón , Dan Nicolaescu , Alexander V. Veidenbaum , Ana-Maria Badulescu Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:1374-1375 [Conf ] Dan Nicolaescu , Alexander V. Veidenbaum , Alexandru Nicolau Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:11064-11069 [Conf ] Ana Azevedo , Arun Kejariwal , Alexander V. Veidenbaum , Alexandru Nicolau High performance annotation-aware JVM for Java cards. [Citation Graph (0, 0)][DBLP ] EMSOFT, 2005, pp:52-61 [Conf ] Milind Girkar , Arun Kejariwal , Xinmin Tian , Hideki Saito , Alexandru Nicolau , Alexander V. Veidenbaum , Constantine D. Polychronopoulos Probablistic Self-Scheduling. [Citation Graph (0, 0)][DBLP ] Euro-Par, 2006, pp:253-264 [Conf ] Sudeep Pasricha , Alexander V. Veidenbaum Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches. [Citation Graph (0, 0)][DBLP ] ICCD, 2003, pp:526-531 [Conf ] Marco A. Ramírez , Adrián Cristal , Mateo Valero , Alexander V. Veidenbaum , Luis Villa A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:647-653 [Conf ] Alexander V. Veidenbaum , Dan Nicolaescu Low Energy, Highly-Associative Cache Design for Embedded Processors. [Citation Graph (0, 0)][DBLP ] ICCD, 2004, pp:332-335 [Conf ] Yung-Chin Chen , Alexander V. Veidenbaum Performance Evaluation of Memory Caches in Multiprocessors. [Citation Graph (0, 0)][DBLP ] ICPP, 1993, pp:184-187 [Conf ] Hoichi Cheong , Alexander V. Veidenbaum Stale Data Detection and Coherence Enforcement Using Flow Analysis. [Citation Graph (0, 0)][DBLP ] ICPP (1), 1988, pp:138-145 [Conf ] Kyle Gallivan , William Jalby , Stephen W. Turner , Alexander V. Veidenbaum , Harry A. G. Wijshoff Preliminary Performance Analysis of the Cedar Multiprocessor Memory System. [Citation Graph (0, 0)][DBLP ] ICPP (1), 1991, pp:71-75 [Conf ] Edward H. Gornish , Alexander V. Veidenbaum An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] ICPP, 1994, pp:281-284 [Conf ] Elana D. Granston , Alexander V. Veidenbaum An Integrated Hardware/Software Solution for Effective Management of Local Storage in High-Performance Systems. [Citation Graph (0, 0)][DBLP ] ICPP (2), 1991, pp:83-90 [Conf ] Sunil Kim , Alexander V. Veidenbaum Stride-directed Prefetching for Secondary Caches. [Citation Graph (0, 0)][DBLP ] ICPP, 1997, pp:314-0 [Conf ] Jeff Konicek , Tracy Tilton , Alexander V. Veidenbaum , Chuan-Qi Zhu , Edward S. Davidson , Ruppert A. Downing , Michael J. Haney , Manish Sharma , Pen-Chung Yew , P. Michael Farmwald , David J. Kuck , Daniel M. Lavery , Robert A. Lindsey , D. Pointer , John T. Andrews , Thomas Beck , T. Murphy , Stephen W. Turner , Nancy J. Warter The Organization of the Cedar System. [Citation Graph (0, 0)][DBLP ] ICPP (1), 1991, pp:49-56 [Conf ] Alexander V. Veidenbaum A Compiler-Assisted Cache Coherence Solution for Multiprcessors. [Citation Graph (0, 0)][DBLP ] ICPP, 1986, pp:1029-1036 [Conf ] Yung-Chin Chen , Alexander V. Veidenbaum A software coherence scheme with the assistance of directories. [Citation Graph (0, 0)][DBLP ] ICS, 1991, pp:284-294 [Conf ] Hoichi Cheong , Alexander V. Veidenbaum The Performance of Software-managed Multiprocessor Caches on Parallel Numerical Programs. [Citation Graph (0, 0)][DBLP ] ICS, 1987, pp:316-337 [Conf ] Hoichi Cheong , Alexander V. Veidenbaum A version control approach to Cache coherence. [Citation Graph (0, 0)][DBLP ] ICS, 1989, pp:322-330 [Conf ] Rubén González , Adrián Cristal , Miquel Pericàs , Mateo Valero , Alexander V. Veidenbaum An asymmetric clustered processor based on value content. [Citation Graph (0, 0)][DBLP ] ICS, 2005, pp:61-70 [Conf ] Edward H. Gornish , Elana D. Granston , Alexander V. Veidenbaum Compiler-directed data prefetching in multiprocessors with memory hierarchies. [Citation Graph (0, 0)][DBLP ] ICS, 1990, pp:354-368 [Conf ] Stephen W. Turner , Alexander V. Veidenbaum Performance of a shared memory system for vector multiprocessors. [Citation Graph (0, 0)][DBLP ] ICS, 1988, pp:315-325 [Conf ] Alexander V. Veidenbaum , Weiyu Tang , Rajesh K. Gupta , Alexandru Nicolau , Xiaomei Ji Adapting cache line size to application behavior. [Citation Graph (0, 0)][DBLP ] International Conference on Supercomputing, 1999, pp:145-154 [Conf ] Arun Kejariwal , Xinmin Tian , Wei Li , Milind Girkar , Sergey Kozhukhov , Hideki Saito , Utpal Banerjee , Alexandru Nicolau , Alexander V. Veidenbaum , Constantine D. Polychronopoulos On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings. [Citation Graph (0, 0)][DBLP ] ICS, 2006, pp:24- [Conf ] Dan Nicolaescu , Xiaomei Ji , Alexander V. Veidenbaum , Alexandru Nicolau , Rajesh K. Gupta Compiler-Directed Cache Line Size Adaptivity. [Citation Graph (0, 0)][DBLP ] Intelligent Memory Systems, 2000, pp:183-187 [Conf ] John D. Bruner , Hoichi Cheong , Alexander V. Veidenbaum , Pen-Chung Yew Chief: A Parallel Simulation Environment for Parallel Systems. [Citation Graph (0, 0)][DBLP ] IPPS, 1991, pp:568-575 [Conf ] Rubén González , Adrián Cristal , Daniel Ortega , Alexander V. Veidenbaum , Mateo Valero A Content Aware Integer Register File Organization. [Citation Graph (0, 0)][DBLP ] ISCA, 2004, pp:314-324 [Conf ] David J. Kuck , Edward S. Davidson , Duncan H. Lawrie , Ahmed H. Sameh , Chuan-Qi Zhu , Alexander V. Veidenbaum , Jeff Konicek , Pen-Chung Yew , Kyle Gallivan , William Jalby , Harry A. G. Wijshoff , Randall Bramley , U. M. Yang , Perry A. Emrath , David A. Padua , Rudolf Eigenmann , Jay Hoeflinger , Greg Jaxon , Zhiyuan Li , T. Murphy , John T. Andrews , Stephen W. Turner The Cedar System and an Initial Performance Study. [Citation Graph (0, 0)][DBLP ] ISCA, 1993, pp:213-223 [Conf ] Hoichi Cheong , Alexander V. Veidenbaum A Cache Coherence Scheme With Fast Selective Invalidation. [Citation Graph (0, 0)][DBLP ] ISCA, 1988, pp:299-307 [Conf ] Alexander V. Veidenbaum , Pen-Chung Yew , David J. Kuck , Constantine D. Polychronopoulos , David A. Padua , Edward S. Davidson , Kyle Gallivan Retrospective: The Cedar System. [Citation Graph (0, 0)][DBLP ] 25 Years ISCA: Retrospectives and Reprints, 1998, pp:89-91 [Conf ] Xiaomei Ji , Dan Nicolaescu , Alexander V. Veidenbaum , Alexandru Nicolau , Rajesh K. Gupta Compiler-Directed Cache Assist Adaptivity. [Citation Graph (0, 0)][DBLP ] ISHPC, 2000, pp:88-104 [Conf ] Marco A. Ramírez , Adrián Cristal , Alexander V. Veidenbaum , Luis Villa , Mateo Valero A Simple Low-Energy Instruction Wakeup Mechanism. [Citation Graph (0, 0)][DBLP ] ISHPC, 2003, pp:99-112 [Conf ] Alexander V. Veidenbaum Instruction Cache Prefetching Using Multilevel Branch Prediction. [Citation Graph (0, 0)][DBLP ] ISHPC, 1997, pp:51-70 [Conf ] Weiyu Tang , Alexander V. Veidenbaum , Alexandru Nicolau , Rajesh K. Gupta Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption. [Citation Graph (0, 0)][DBLP ] ISHPC, 2002, pp:120-132 [Conf ] Dan Nicolaescu , Alexander V. Veidenbaum , Alexandru Nicolau Reducing data cache energy consumption via cached load/store queue. [Citation Graph (0, 0)][DBLP ] ISLPED, 2003, pp:252-257 [Conf ] Paolo D'Alberto , Alexandru Nicolau , Alexander V. Veidenbaum A Data Cache with Dynamic Mapping. [Citation Graph (0, 0)][DBLP ] LCPC, 2003, pp:436-450 [Conf ] Dan Nicolaescu , Alexander V. Veidenbaum , Alexandru Nicolau Caching Values in the Load Store Queue. [Citation Graph (0, 0)][DBLP ] MASCOTS, 2004, pp:580-587 [Conf ] Miquel Pericàs , Rubén González , Adrián Cristal , Alexander V. Veidenbaum , Mateo Valero An Optimized Front-End Physical Register File with Banking and Writeback Filtering. [Citation Graph (0, 0)][DBLP ] PACS, 2004, pp:1-14 [Conf ] Arun Kejariwal , Xinmin Tian , Milind Girkar , Wei Li , Sergey Kozhukhov , Utpal Banerjee , Alexandru Nicolau , Alexander V. Veidenbaum , Constantine D. Polychronopoulos Tight analysis of the performance potential of thread speculation using spec CPU 2006. [Citation Graph (0, 0)][DBLP ] PPOPP, 2007, pp:215-225 [Conf ] Yung-Chin Chen , Alexander V. Veidenbaum Comparison and analysis of software and directory coherence schemes. [Citation Graph (0, 0)][DBLP ] SC, 1991, pp:818-829 [Conf ] Yung-Chin Chen , Alexander V. Veidenbaum An Effective Write Policy for Software Coherence Schemes. [Citation Graph (0, 0)][DBLP ] SC, 1992, pp:661-672 [Conf ] Elana D. Granston , Alexander V. Veidenbaum Detecting redundant accesses to array data. [Citation Graph (0, 0)][DBLP ] SC, 1991, pp:854-865 [Conf ] Stephen W. Turner , Alexander V. Veidenbaum Scalability of the Cedar system. [Citation Graph (0, 0)][DBLP ] SC, 1994, pp:247-254 [Conf ] Sunil Kim , Alexander V. Veidenbaum On Shortest Path Routing in Single Stage Shuffle-Exchange Networks. [Citation Graph (0, 0)][DBLP ] SPAA, 1995, pp:298-307 [Conf ] Hoichi Cheong , Alexander V. Veidenbaum Compiler-Directed Cache Management in Multiprocessors. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 1990, v:23, n:6, pp:39-47 [Journal ] Alex Orailoglu , Alexander V. Veidenbaum Guest Editors' Introduction: Application-Specific Microprocessors. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2003, v:20, n:1, pp:6-7 [Journal ] José L. Ayala , Alexander V. Veidenbaum , Marisa Luisa López-Vallejo Power-Aware Compilation for Register File Energy Reduction. [Citation Graph (0, 0)][DBLP ] International Journal of Parallel Programming, 2003, v:31, n:6, pp:451-467 [Journal ] Edward H. Gornish , Alexander V. Veidenbaum An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] International Journal of Parallel Programming, 1999, v:27, n:1, pp:35-70 [Journal ] Alexander V. Veidenbaum Guest Editor's Introduction. [Citation Graph (0, 0)][DBLP ] International Journal of Parallel Programming, 2001, v:29, n:5, pp:461-462 [Journal ] Alexander V. Veidenbaum Guest Editor's Introduction. [Citation Graph (0, 0)][DBLP ] International Journal of Parallel Programming, 2002, v:30, n:4, pp:223-224 [Journal ] Alexander V. Veidenbaum Guest Editor's Introduction: Application-Specific Processors. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2004, v:24, n:3, pp:8-9 [Journal ] Sunil Kim , Alexander V. Veidenbaum Interconnection network organization and its impact on performance and cost in shared memory multiprocessors. [Citation Graph (0, 0)][DBLP ] Parallel Computing, 1999, v:25, n:3, pp:283-309 [Journal ] Paolo D'Alberto , Alexandru Nicolau , Alexander V. Veidenbaum , Rajesh K. Gupta Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2005, v:54, n:2, pp:185-197 [Journal ] Sunil Kim , Alexander V. Veidenbaum On Interaction between Interconnection Network Design and Latency Hiding Techniques in Multiprocessors. [Citation Graph (0, 0)][DBLP ] The Journal of Supercomputing, 2000, v:16, n:3, pp:197-216 [Journal ] Carmen Badea , Alexandru Nicolau , Alexander V. Veidenbaum A simplified java bytecode compilation system for resource-constrained embedded processors. [Citation Graph (0, 0)][DBLP ] CASES, 2007, pp:218-228 [Conf ] Gerolf Hoflehner , Darshan Desai , Daniel M. Lavery , Alexandru Nicolau , Alexander V. Veidenbaum Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture. [Citation Graph (0, 0)][DBLP ] SIGMETRICS, 2007, pp:361-362 [Conf ] Weiyu Tang , Arun Kejariwal , Alexander V. Veidenbaum , Alexandru Nicolau A predictive decode filter cache for reducing power consumption in embedded processors. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:2, pp:- [Journal ] Multiple sleep mode leakage control for cache peripheral circuits in embedded processors. [Citation Graph (, )][DBLP ] Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. [Citation Graph (, )][DBLP ] Exploitation of nested thread-level speculative parallelism on multi-core systems. [Citation Graph (, )][DBLP ] Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency. [Citation Graph (, )][DBLP ] RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor. [Citation Graph (, )][DBLP ] Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy. [Citation Graph (, )][DBLP ] Reducing leakage power in peripheral circuits of L2 caches. [Citation Graph (, )][DBLP ] ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits. [Citation Graph (, )][DBLP ] Adaptive techniques for leakage power management in L2 cache peripheral circuits. [Citation Graph (, )][DBLP ] Efficient Scheduling of Nested Parallel Loops on Multi-Core Systems. [Citation Graph (, )][DBLP ] Synchronization optimizations for efficient execution on multi-cores. [Citation Graph (, )][DBLP ] Power-aware load balancing of large scale MPI applications. [Citation Graph (, )][DBLP ] A Two-Level Load/Store Queue Based on Execution Locality. [Citation Graph (, )][DBLP ] Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. [Citation Graph (, )][DBLP ] Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks. [Citation Graph (, )][DBLP ] Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors. [Citation Graph (, )][DBLP ] Impact of JVM superoperators on energy consumption in resource-constrained embedded systems. [Citation Graph (, )][DBLP ] A distributed processor state management architecture for large-window processors. [Citation Graph (, )][DBLP ] Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements. [Citation Graph (, )][DBLP ] Cache-aware iteration space partitioning. [Citation Graph (, )][DBLP ] Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® CoreTM 2 Duo processor. [Citation Graph (, )][DBLP ] A centralized cache miss driven technique to improve processor power dissipation. [Citation Graph (, )][DBLP ] On the efficacy of call graph-level thread-level speculation. [Citation Graph (, )][DBLP ] Performance Characterization of Itanium® 2-Based Montecito Processor. [Citation Graph (, )][DBLP ] Cache-aware partitioning of multi-dimensional iteration spaces. [Citation Graph (, )][DBLP ] Search in 0.004secs, Finished in 0.605secs