The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Todd M. Austin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Artur Klauser, Todd M. Austin, Dirk Grunwald, Brad Calder
    Dynamic Hammock Predication for Non-Predicated Instruction Set Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:278-285 [Conf]
  2. Todd M. Austin, Valeria Bertacco, David Blaauw, Trevor N. Mudge
    Opportunities and challenges for better than worst-case design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:2-7 [Conf]
  3. Ilya Wagner, Valeria Bertacco, Todd M. Austin
    Depth-driven verification of simultaneous interfaces. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:442-447 [Conf]
  4. Jerome Burke, John McDonald, Todd M. Austin
    Architectural Support for Fast Symmetric-Key Cryptography. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2000, pp:178-189 [Conf]
  5. Brad Calder, Chandra Krintz, Simmi John, Todd M. Austin
    Cache-Conscious Data Placement. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1998, pp:139-149 [Conf]
  6. Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd M. Austin
    Ultra low-cost defect protection for microprocessor pipelines. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:73-82 [Conf]
  7. Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David Blaauw
    A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:249-256 [Conf]
  8. Rajeev Krishna, Scott A. Mahlke, Todd M. Austin
    Architectural optimizations for low-power, real-time speech recognition. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:220-231 [Conf]
  9. Chris Weaver, Rajeev Krishna, Lisa Wu, Todd M. Austin
    Application specific architectures: a recipe for fast, flexible and power efficient designs. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:181-185 [Conf]
  10. Rajeev Krishna, Scott A. Mahlke, Todd M. Austin
    Memory system design space exploration for low-power, real-time speech recognition. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:140-145 [Conf]
  11. Todd M. Austin
    Designing robust microarchitectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:78- [Conf]
  12. Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge
    Circuit-aware architectural simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:305-310 [Conf]
  13. Maher N. Mneimneh, Fadi A. Aloul, Chris Weaver, Saugata Chatterjee, Karem A. Sakallah, Todd M. Austin
    Scalable Hybrid Verification of Complex Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:41-46 [Conf]
  14. Ilya Wagner, Valeria Bertacco, Todd M. Austin
    StressTest: an automatic approach to test generation via activity monitors. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:783-788 [Conf]
  15. Ilya Wagner, Valeria Bertacco, Todd M. Austin
    Shielding against design flaws with field repairable control logic. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:344-347 [Conf]
  16. Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin
    DVS for On-Chip Bus Designs Based on Timing Error Correction. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:80-85 [Conf]
  17. Chris Weaver, Todd M. Austin
    A Fault Tolerant Approach to Microprocessor Design. [Citation Graph (0, 0)][DBLP]
    DSN, 2001, pp:411-420 [Conf]
  18. Todd M. Austin, Valeria Bertacco
    Deployment of Better Than Worst-Case Design: Solutions and Needs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:550-558 [Conf]
  19. Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary S. Tyson, Todd M. Austin
    Classifying load and store instructions for memory renaming. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:399-407 [Conf]
  20. Todd M. Austin, Dionisios N. Pnevmatikatos, Gurindar S. Sohi
    Streamlining Data Cache Access with Fast Address Calculation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:369-380 [Conf]
  21. Todd M. Austin, Gurindar S. Sohi
    Dynamic Dependency Analysis of Ordinary Programs. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:342-351 [Conf]
  22. Todd M. Austin, Gurindar S. Sohi
    High-Bandwidth Address Translation for Multiple-Issue Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:158-167 [Conf]
  23. Dan Ernst, Todd M. Austin
    Efficient Dynamic Scheduling Through Tag Elimination. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:37-46 [Conf]
  24. Dan Ernst, Andrew Hamel, Todd M. Austin
    Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:253-262 [Conf]
  25. Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David Blaauw
    Energy Optimization of Subthreshold-Voltage Sensor Network Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:197-207 [Conf]
  26. Glenn Reinman, Todd M. Austin, Brad Calder
    A Scalable Front-End Architecture for Fast Instruction Delivery. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:234-245 [Conf]
  27. Lisa Wu, Chris Weaver, Todd M. Austin
    CryptoManiac: a fast flexible architecture for secure communication. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:110-119 [Conf]
  28. Glenn Reinman, Brad Calder, Todd M. Austin
    High Performance and Energy Efficient Serial Prefetch Architecture. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:146-159 [Conf]
  29. Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge
    Reducing pipeline energy demands with local DVS and dynamic retiming. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:319-324 [Conf]
  30. Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge
    Microarchitectural power modeling techniques for deep sub-micron microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:212-217 [Conf]
  31. David Roberts, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner
    Error Analysis for the Support of Robust Voltage Scaling. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:65-70 [Conf]
  32. Todd M. Austin
    DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:196-207 [Conf]
  33. Todd M. Austin, Gurindar S. Sohi
    Zero-cycle loads: microarchitecture support for reducing load latency. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:82-92 [Conf]
  34. Saugata Chatterjee, Chris Weaver, Todd M. Austin
    Efficient checker processor design. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:87-97 [Conf]
  35. Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge
    Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:7-18 [Conf]
  36. Shubhendu S. Mukherjee, Christopher Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin
    A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:29-42 [Conf]
  37. Eric Larson, Todd M. Austin
    Compiler controlled value prediction using branch predictor based confidence. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:327-336 [Conf]
  38. Glenn Reinman, Brad Calder, Todd M. Austin
    Fetch Directed Instruction Prefetching. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:16-27 [Conf]
  39. Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin
    On High-Bandwidth Data Cache Design for Multi-Issue Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:46-56 [Conf]
  40. Gary S. Tyson, Todd M. Austin
    Improving the Accuracy and Performance of Memory Communication Through Renaming. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:218-227 [Conf]
  41. Todd M. Austin, Scott E. Breach, Gurindar S. Sohi
    Efficient Detection of All Pointer and Array Access Errors. [Citation Graph (0, 0)][DBLP]
    PLDI, 1994, pp:290-301 [Conf]
  42. Todd M. Austin
    Robust low power computing in the nanoscale era. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:6- [Conf]
  43. Todd M. Austin
    Razor: a low-power pipeline based on circuit-level timing speculation. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:13- [Conf]
  44. Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner
    Making Typical Silicon Matter with Razor. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:3, pp:57-65 [Journal]
  45. Todd M. Austin, David Blaauw, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Wayne Wolf
    Mobile Supercomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:5, pp:81-83 [Journal]
  46. Todd M. Austin, Eric Larson, Dan Ernst
    SimpleScalar: An Infrastructure for Computer System Modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:2, pp:59-67 [Journal]
  47. Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan
    Leakage Current: Moore's Law Meets Static Power. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:12, pp:68-75 [Journal]
  48. Shubhendu S. Mukherjee, Sarita V. Adve, Todd M. Austin, Joel S. Emer, Peter S. Magnusson
    Performance Simulation Tools. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:2, pp:38-39 [Journal]
  49. Todd M. Austin
    Design for Verification? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:4, pp:80- [Journal]
  50. Gary S. Tyson, Todd M. Austin
    Memory Renaming: Fast, Early and Accurate Processing of Memory Communication. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:5, pp:357-380 [Journal]
  51. Todd M. Austin
    DIVA: A Dynamic Approach to Microprocessor Verification. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  52. Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner
    Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:10-20 [Journal]
  53. Shubhendu S. Mukherjee, Chris Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin
    Measuring Architectural Vulnerability Factors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:70-75 [Journal]
  54. Doug Burger, Todd M. Austin, Stephen W. Keckler
    Recent extensions to the SimpleScalar tool suite. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS Performance Evaluation Review, 2004, v:31, n:4, pp:4-7 [Journal]
  55. Glenn Reinman, Brad Calder, Todd M. Austin
    Optimizations Enabled by a Decoupled Front-End Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:4, pp:338-355 [Journal]
  56. Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd M. Austin
    Low-cost protection for SER upsets and silicon defects. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1146-1151 [Conf]
  57. Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd M. Austin
    Architectural implications of brick and mortar silicon manufacturing. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:244-253 [Conf]
  58. Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin
    DVS for On-Chip Bus Designs Based on Timing Error Correction [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  59. Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky
    Architecting a reliable CMP switch architecture. [Citation Graph (0, 0)][DBLP]
    TACO, 2007, v:4, n:1, pp:- [Journal]

  60. Reliability-aware data placement for partial memory protection in embedded processors. [Citation Graph (, )][DBLP]


  61. What input-language is the best choice for high level synthesis (HLS)? [Citation Graph (, )][DBLP]


  62. Using introspective software-based testing for post-silicon debug and repair. [Citation Graph (, )][DBLP]


  63. Fault-based attack of RSA authentication. [Citation Graph (, )][DBLP]


  64. BulletProof: a defect-tolerant CMP switch architecture. [Citation Graph (, )][DBLP]


  65. CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework. [Citation Graph (, )][DBLP]


  66. Polymorphic On-Chip Networks. [Citation Graph (, )][DBLP]


  67. On the rules of low-power design (and how to break them). [Citation Graph (, )][DBLP]


  68. Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. [Citation Graph (, )][DBLP]


  69. Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. [Citation Graph (, )][DBLP]


  70. Testudo: Heavyweight security analysis via statistical sampling. [Citation Graph (, )][DBLP]


  71. Reliable Systems on Unreliable Fabrics. [Citation Graph (, )][DBLP]


Search in 0.006secs, Finished in 0.009secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002