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Hanpei Koike: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yuetsu Kodama, Hirofumi Sakane, Hanpei Koike, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi
    Parallel Execution of Radix Sort Program Using Fine-Grain Communication. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1997, pp:136-145 [Conf]
  2. Hanpei Koike, Hidehiko Tanaka
    Multi-Context Processing and Data Balancing Mechanism of the Parallel Inference Machine PIE64. [Citation Graph (0, 0)][DBLP]
    FGCS, 1988, pp:970-977 [Conf]
  3. Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka
    UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64. [Citation Graph (0, 0)][DBLP]
    FGCS, 1992, pp:715-722 [Conf]
  4. Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
    Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:257- [Conf]
  5. Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
    Evaluation of granularity on threshold voltage control in flex power FPGA. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:223- [Conf]
  6. Yohei Matsumoto, Hanpei Koike, Akira Masaki
    FPGAs with multidimensional mesh topology. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:223- [Conf]
  7. Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
    Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:169-177 [Conf]
  8. Lu Xu, Hanpei Koike, Hidehiko Tanaka
    Distributed Garbage Collection for the Parallel Inference Machine PIE64. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1989, pp:1161-1166 [Conf]
  9. Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka
    The Instruction Set Architecture of the Inference Processor UNIRED II. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:117-128 [Conf]
  10. Hidemoto Nakada, Takuya Araki, Hanpei Koike, Hidehiko Tanaka
    A Fleng Compiler for PIE64. [Citation Graph (0, 0)][DBLP]
    IFIP PACT, 1994, pp:257-266 [Conf]
  11. Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
    Multiple Threads in Cyclic Register Windows. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:131-142 [Conf]
  12. Hanpei Koike, Hidehiko Tanaka
    Fast Execution Mechanisms of Parallel Inference Engine PIE: PIEpelined Goal Rewriting and Goal Multicasting. [Citation Graph (0, 0)][DBLP]
    LP, 1986, pp:159-169 [Conf]
  13. Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
    Architecture of Parallel Management Kernel for PIE64. [Citation Graph (0, 0)][DBLP]
    PARLE, 1992, pp:685-700 [Conf]
  14. Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka
    Control and Data Flow Visualization for Parallel Logic Programs on a Multi-window Debugger HyperDEBU. [Citation Graph (0, 0)][DBLP]
    PARLE, 1993, pp:414-425 [Conf]
  15. Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka
    HyperDEBU: A Multiwindow Debugger for Parallel Logic Programs. [Citation Graph (0, 0)][DBLP]
    Programming Environments for Parallel Computing, 1992, pp:87-105 [Conf]
  16. Hayato Yamana, Hanpei Koike, Yuetsu Kodama, Hirofumi Sakane, Yoshinori Yamaguchi
    Fast Speculative Search Engine on the Highly Parallel Computer EM-X. [Citation Graph (0, 0)][DBLP]
    SIGIR, 1998, pp:390- [Conf]
  17. Yasuo Hidaka, Hanpei Koike, Jun'ichi Tatemura, Hidehiko Tanaka
    A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages. [Citation Graph (0, 0)][DBLP]
    ISLP, 1991, pp:470-484 [Conf]
  18. Lu Xu, Hanpei Koike, Hidehiko Tanaka
    Distributed Garbage Collection for the Parallel Inference Engine PIE64. [Citation Graph (0, 0)][DBLP]
    NACLP, 1989, pp:922-941 [Conf]
  19. Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka
    A Performance Debugger for a Parallel Logic Programming Language Fleng. [Citation Graph (0, 0)][DBLP]
    Theory and Practice of Parallel Programming, 1994, pp:284-299 [Conf]
  20. Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka
    UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64. [Citation Graph (0, 0)][DBLP]
    New Generation Comput., 1993, v:11, n:3, pp:251-269 [Journal]

  21. High-speed low-power FinFET based domino logic. [Citation Graph (, )][DBLP]


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