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Shuichi Sakai:
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Publications of Author
- Yuetsu Kodama, Hirofumi Sakane, Hanpei Koike, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi
Parallel Execution of Radix Sort Program Using Fine-Grain Communication. [Citation Graph (0, 0)][DBLP] IEEE PACT, 1997, pp:136-145 [Conf]
- Antonio Magnaghi, Shuichi Sakai, Hidehiko Tanaka
Inter-procedural Analysis for Parallelization of Java Programs. [Citation Graph (0, 0)][DBLP] ACPC, 1999, pp:594-595 [Conf]
- Koichi Miura, Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka
Associating Cooking Video Segments with Preparation Steps. [Citation Graph (0, 0)][DBLP] CIVR, 2003, pp:174-183 [Conf]
- Chitaka Iwama, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka
Improving Conditional Branch Prediction on Speculative Multithreading Architectures. [Citation Graph (0, 0)][DBLP] Euro-Par, 2001, pp:413-417 [Conf]
- Hideyuki Miura, Luong Dinh Hung, Chitaka Iwama, Daisuke Tashiro, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka
Compiler-Assisted Thread Level Control Speculation. [Citation Graph (0, 0)][DBLP] Euro-Par, 2003, pp:603-608 [Conf]
- Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi
Evaluation of the EM-4 Highly Parallel Computer using a Game Tree Searching Problem. [Citation Graph (0, 0)][DBLP] FGCS, 1992, pp:731-738 [Conf]
- Yoshimitsu Yanagawa, Luong Dinh Hung, Chitaka Iwama, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka
Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors. [Citation Graph (0, 0)][DBLP] HiPC, 2003, pp:393-404 [Conf]
- Shuichi Sakai
Overview of RWC Massively Parallel Computer Project. [Citation Graph (0, 0)][DBLP] HPDC, 1994, pp:5- [Conf]
- Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag. [Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:342-350 [Conf]
- Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi
Design and Implementation of a Versatile Interconnection Network in the EM-4. [Citation Graph (0, 0)][DBLP] ICPP (1), 1991, pp:426-430 [Conf]
- Yuetsu Kodama, Yasuhito Koumura, Mitsuhisa Sato, Hirohumi Sakane, Shuichi Sakai, Yoshinori Yamaguchi
EMC-Y: Parallel Processing Element Optimizing Communication and Computation. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:167-174 [Conf]
- Shuichi Sakai, Kazuaki Okamoto, Hiroshi Matsuoka, Hideo Hirono, Yuetsu Kodama, Mitsuhisa Sato
Super-Threading: Architectural and Software Mechanisms for Optimizing Parallel Computation. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:251-260 [Conf]
- Hayato Yamana, Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Shuichi Sakai, Yoshinori Yamaguchi
A Macrotask-level Unlimited Speculative Execution on Multiprocessors. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1995, pp:328-337 [Conf]
- Toshitsugu Yuba, Toshio Shimada, Yoshinori Yamaguchi, Kei Hiraki, Shuichi Sakai
Dataflow computer development in Japan. [Citation Graph (0, 0)][DBLP] ICS, 1990, pp:140-147 [Conf]
- Yoshinori Yamaguchi, Shuichi Sakai, Kei Hiraki, Yuetsu Kodama
An Architectural Disgn of a Highly Parallel Dataflow Machine. [Citation Graph (0, 0)][DBLP] IFIP Congress, 1989, pp:1155-1160 [Conf]
- Mitsuhisa Sato, Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi
EM-C: Programming with Explicit Parallelism and Locality for EM-4 Multiprocessor. [Citation Graph (0, 0)][DBLP] IFIP PACT, 1994, pp:3-14 [Conf]
- Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka
Relating Graphical Features with Concept Classes for Automatic News Video Indexing. [Citation Graph (0, 0)][DBLP] Intelligent Information Integration, 1999, pp:- [Conf]
- Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
Experience with Fine-Grain Communication in EM-X Multiprocessor for Parallel Sparse Matrix Computation. [Citation Graph (0, 0)][DBLP] IPPS, 1997, pp:242-248 [Conf]
- Mitsuhisa Sato, Yuetsu Kodama, Yoshinori Yamaguchi, Shuichi Sakai
Experience with Executing Shared Memory Programs using Fine-Grain Communication and Multithreading in EM-4. [Citation Graph (0, 0)][DBLP] IPPS, 1994, pp:630-636 [Conf]
- Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi
Prototype Implementation of a Highly Parallel Dataflow Machine EM-4. [Citation Graph (0, 0)][DBLP] IPPS, 1991, pp:278-286 [Conf]
- Kenji Toda, Kenji Nishida, Yoshinobu Uchibori, Shuichi Sakai, Toshio Shimada
Parallel Multi-Context Architecture with High-Speed Synchronization Mechanism. [Citation Graph (0, 0)][DBLP] IPPS, 1991, pp:336-343 [Conf]
- Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
The EM-X Parallel Computer: Architecture and Basic Performance. [Citation Graph (0, 0)][DBLP] ISCA, 1995, pp:14-23 [Conf]
- Shuichi Sakai, Yoshinori Yamaguchi, Kei Hiraki, Yuetsu Kodama, Toshitsugu Yuba
An Architecture of a Dataflow Single Chip Processor. [Citation Graph (0, 0)][DBLP] ISCA, 1989, pp:46-53 [Conf]
- Mitsuhisa Sato, Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi, Yasuhito Koumura
Thread-based Programming for the EM-4 Hybrid Dataflow Machine. [Citation Graph (0, 0)][DBLP] ISCA, 1992, pp:146-155 [Conf]
- Shuichi Sakai
CMP on SoC: Architect's View. [Citation Graph (0, 0)][DBLP] ISSS, 2002, pp:101-102 [Conf]
- Atsushi Hori, Takashi Yokota, Yutaka Ishikawa, Shuichi Sakai, Hiroki Konaka, Munenori Maeda, Takashi Tomokiyo, Jörg Nolte, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono
Time Space Sharing Scheduling and Architectural Support. [Citation Graph (0, 0)][DBLP] JSSPP, 1995, pp:92-105 [Conf]
- Reiko Hamada, Ichiro Ide, Shuichi Sakai
Associating cooking video with related textbook. [Citation Graph (0, 0)][DBLP] ACM Multimedia Workshops, 2000, pp:237-241 [Conf]
- Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka
Associating video with related documents. [Citation Graph (0, 0)][DBLP] ACM Multimedia (2), 1999, pp:17-20 [Conf]
- Reiko Hamada, Jun Okabe, Ichiro Ide, Shin'ichi Satoh, Shuichi Sakai, Hidehiko Tanaka
Cooking navi: assistant for daily cooking in kitchen. [Citation Graph (0, 0)][DBLP] ACM Multimedia, 2005, pp:371-374 [Conf]
- Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka
Scene identification in news video by character region segmentation. [Citation Graph (0, 0)][DBLP] ACM Multimedia Workshops, 2000, pp:195-200 [Conf]
- Reiko Hamada, Koichi Miura, Ichiro Ide, Shin'ichi Satoh, Shuichi Sakai, Hidehiko Tanaka
Multimedia Integration for Cooking Video Indexing. [Citation Graph (0, 0)][DBLP] PCM (2), 2004, pp:657-664 [Conf]
- Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
SEVA: A Soft-Error- and Variation-Aware Cache Architecture. [Citation Graph (0, 0)][DBLP] PRDC, 2006, pp:47-54 [Conf]
- Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai
Base Address Recognition with Data Flow Tracking for Injection Attack Detection. [Citation Graph (0, 0)][DBLP] PRDC, 2006, pp:165-172 [Conf]
- Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi
Load balancing by function distribution on the EM-4 prototype. [Citation Graph (0, 0)][DBLP] SC, 1991, pp:522-531 [Conf]
- Andrew Sohn, Mitsuhisa Sato, Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi
Nonnumeric search results on the EM-4 distributed-memory multiprocessor. [Citation Graph (0, 0)][DBLP] SC, 1994, pp:301-310 [Conf]
- Andrew Sohn, Yuetsu Kodama, Jui Ku, Mitsuhisa Sato, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
Fine-Grain Multithreading with the EM-X Multiprocessor. [Citation Graph (0, 0)][DBLP] SPAA, 1997, pp:189-198 [Conf]
- Shuichi Sakai, Hiroshi Matsuoka, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota
RICA: Reduced Interprocessor-Communication Architecture - Concept and Mechanisms. [Citation Graph (0, 0)][DBLP] SPDP, 1993, pp:122-127 [Conf]
- Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Yoshinori Yamaguchi, Shuichi Sakai
Programming with Distributed Data Structure for EM-X Multiprocessor. [Citation Graph (0, 0)][DBLP] Theory and Practice of Parallel Programming, 1994, pp:472-483 [Conf]
- Masaaki Honda, Takeo Igarashi, Hidehiko Tanaka, Shuichi Sakai
Integrated Manipulation: Context-Aware Manipulation of 2D Diagrams. [Citation Graph (0, 0)][DBLP] ACM Symposium on User Interface Software and Technology, 1999, pp:159-160 [Conf]
- Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka
Structural analysis of cooking preparation steps in Japanese. [Citation Graph (0, 0)][DBLP] IRAL, 2000, pp:157-164 [Conf]
- Shuichi Sakai, Mitsunori Togasaki, Koichi Yamazaki
A note on greedy algorithms for the maximum weighted independent set problem. [Citation Graph (0, 0)][DBLP] Discrete Applied Mathematics, 2003, v:126, n:2-3, pp:313-322 [Journal]
- Kazuaki Okamoto, Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi
Methodologies in development and testing of the dataflow machine EM-4. [Citation Graph (0, 0)][DBLP] Parallel Computing, 1992, v:18, n:8, pp:901-912 [Journal]
- Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi
Design and Implementation of a Circular Omega Network in the EM-4. [Citation Graph (0, 0)][DBLP] Parallel Computing, 1993, v:19, n:2, pp:125-142 [Journal]
- Shuichi Sakai, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hiroshi Matsuoka, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota
Reduced Interprocessor-Communication Architecture and its Implementation on EM-4. [Citation Graph (0, 0)][DBLP] Parallel Computing, 1995, v:21, n:5, pp:753-769 [Journal]
- Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka
Compilation of dictionaries for semantic attribute analysis of television news captions. [Citation Graph (0, 0)][DBLP] Systems and Computers in Japan, 2003, v:34, n:12, pp:32-44 [Journal]
- Koichi Miura, Motomu Takano, Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka
Associating semantically structured cooking videos with their preparation steps. [Citation Graph (0, 0)][DBLP] Systems and Computers in Japan, 2005, v:36, n:2, pp:51-62 [Journal]
- Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai
Utilization of SECDED for soft error and variation-induced defect tolerance in caches. [Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1134-1139 [Conf]
Dependable VLSI: device, design and architecture: how should they cooperate? [Citation Graph (, )][DBLP]
Dynamic Estimation of Task Level Parallelism with Operating System Support. [Citation Graph (, )][DBLP]
String-Wise Information Flow Tracking against Script Injection Attacks. [Citation Graph (, )][DBLP]
Low-Overhead Architecture for Security Tag. [Citation Graph (, )][DBLP]
A priority forwarding scheme for real-time multistage interconnection networks. [Citation Graph (, )][DBLP]
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