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Norman P. Jouppi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
    Core architecture optimization for heterogeneous chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:23-32 [Conf]
  2. John L. Hennessy, Norman P. Jouppi, Forest Baskett, Thomas R. Gross, John Gill
    Hardware/Software Tradeoffs for Increased Performance. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:2-11 [Conf]
  3. Norman P. Jouppi, Jonathan Bertoni, David W. Wall
    A Unified Vector/Scalar Floating-Point Architecture. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1989, pp:134-143 [Conf]
  4. Norman P. Jouppi, David W. Wall
    Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1989, pp:272-282 [Conf]
  5. Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Timothy Sherwood, Suleyman Sair
    Improving the performance and power efficiency of shared helpers in CMPs. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:345-356 [Conf]
  6. John L. Hennessy, Norman P. Jouppi, John Gill, Forest Baskett, Alex Strong, Thomas R. Gross, Christopher Rowen, Judson Leonard
    The MIPS Machine. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1982, pp:2-7 [Conf]
  7. Norman P. Jouppi
    First steps towards mutually-immersive mobile telepresence. [Citation Graph (0, 0)][DBLP]
    CSCW, 2002, pp:354-363 [Conf]
  8. Norman P. Jouppi
    The Future Evolution of High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    HiPC, 2004, pp:5- [Conf]
  9. Keith I. Farkas, Norman P. Jouppi, Paul Chow
    How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:78-89 [Conf]
  10. Keith I. Farkas, Norman P. Jouppi, Paul Chow
    Register File Design Considerations in Dynamically Scheduled Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:40-51 [Conf]
  11. Parthasarathy Ranganathan, Norman P. Jouppi
    Enterprise IT Trends and Implications for Architecture Research. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:253-256 [Conf]
  12. Jacob Augustine, Shivarama Rao, Norman P. Jouppi, Subu Iyer
    Region of interest editing of MPEG-2 video streams in the compressed domain. [Citation Graph (0, 0)][DBLP]
    ICME, 2004, pp:559-562 [Conf]
  13. J. Bradley Chen, Anita Borg, Norman P. Jouppi
    A Simulation Based Study of TLB Performance. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:114-123 [Conf]
  14. Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
    Memory-System Design Considerations for Dynamically-Scheduled Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:133-143 [Conf]
  15. Keith I. Farkas, Norman P. Jouppi
    Complexity/Performance Tradeoffs with Non-Blocking Loads. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:211-222 [Conf]
  16. M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas
    The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:14-24 [Conf]
  17. Norman P. Jouppi
    Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:281-289 [Conf]
  18. Norman P. Jouppi
    Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:364-373 [Conf]
  19. Norman P. Jouppi
    Cache Write Policies and Performance. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:191-201 [Conf]
  20. Norman P. Jouppi
    Retrospective: Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:71-73 [Conf]
  21. Norman P. Jouppi
    Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch Buffers. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:388-397 [Conf]
  22. Norman P. Jouppi, Steven J. E. Wilton
    Tradeoffs in Two-Level On-Chip Caching. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:34-45 [Conf]
  23. Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas
    Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:64-75 [Conf]
  24. Subbarao Palacharla, Norman P. Jouppi, James E. Smith
    Complexity-Effective Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:206-218 [Conf]
  25. Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi
    Reconfigurable caches and their application to media processing. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:214-224 [Conf]
  26. Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi
    Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:124-135 [Conf]
  27. Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
    The Multicluster Architecture: Reducing Cycle Time Through Partitioning. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:149-159 [Conf]
  28. Norman P. Jouppi
    The Future Evolution of High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:155- [Conf]
  29. Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen
    Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:81-92 [Conf]
  30. Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen
    Conjoined-Core Chip Multiprocessing. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:195-206 [Conf]
  31. Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Mike Schlansker, Brad Calder
    Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:235-246 [Conf]
  32. Norman P. Jouppi, Subu Iyer, Stan Thomas, April Slayden
    BiReality: mutually-immersive telepresence. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 2004, pp:860-867 [Conf]
  33. Jean-Francois Collard, Norman P. Jouppi, Sami Yehia
    System-wide performance monitors and their application to the optimization of coherent memory accesses. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2005, pp:247-254 [Conf]
  34. Christophe Lemuet, Jack Sampson, Jean-Francois Collard, Norman P. Jouppi
    Architecture - The potential energy efficiency of vector acceleration. [Citation Graph (0, 0)][DBLP]
    SC, 2006, pp:77- [Conf]
  35. Joel McCormack, Ronald N. Perry, Keith I. Farkas, Norman P. Jouppi
    Feline: Fast Elliptical Lines for Anisotropic Texture Mapping. [Citation Graph (0, 0)][DBLP]
    SIGGRAPH, 1999, pp:243-250 [Conf]
  36. Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen
    Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2003, v:2, n:, pp:- [Journal]
  37. John L. Hennessy, Norman P. Jouppi
    Computer Technology and Architecture: An Evolving Interaction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1991, v:24, n:9, pp:18-29 [Journal]
  38. Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan
    Heterogeneous Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:11, pp:32-38 [Journal]
  39. Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
    The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:5, pp:327-356 [Journal]
  40. Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Suleyman Sair, Timothy Sherwood
    Dynamically configurable shared CMP helper engines for improved performance. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:4, pp:70-79 [Journal]
  41. Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen
    Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05). [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:4, pp:4- [Journal]
  42. Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Mike Schlansker
    Fast synchronization for chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:4, pp:64-69 [Journal]
  43. Norman P. Jouppi
    The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:12, pp:1645-1658 [Journal]
  44. Norman P. Jouppi
    Derivation of Signal Flow Direction in MOS VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:480-490 [Journal]
  45. Norman P. Jouppi
    Timing Analysis and Performance Improvement of MOS VLSI Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:650-665 [Journal]
  46. Shekhar Borkar, Norman P. Jouppi, Per Stenström
    Microprocessors in the era of terascale integration. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:237-242 [Conf]
  47. Norman P. Jouppi, Subu Iyer, Wayne Mack, April Slayden Mitchell, Stan Thomas
    A First Generation Mutually-Immersive Mobile Telepresence Surrogate with Automatic Backtracking. [Citation Graph (0, 0)][DBLP]
    ICRA, 2004, pp:1670-1675 [Conf]
  48. Norman P. Jouppi, Stan Thomas
    Telepresence Systems With Automatic Preservation of User Head Height, Local Rotation, and Remote Translation. [Citation Graph (0, 0)][DBLP]
    ICRA, 2005, pp:62-68 [Conf]
  49. Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith
    Configurable isolation: building high availability systems with commodity multi-core processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:470-481 [Conf]

  50. Resilience Challenges for Exascale Systems. [Citation Graph (, )][DBLP]


  51. A High-Speed Optical Multi-Drop Bus for Computer Interconnections. [Citation Graph (, )][DBLP]


  52. A Nanophotonic Interconnect for High-Performance Many-Core Computation. [Citation Graph (, )][DBLP]


  53. PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM. [Citation Graph (, )][DBLP]


  54. Corona: System Implications of Emerging Nanophotonic Technology. [Citation Graph (, )][DBLP]


  55. A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies. [Citation Graph (, )][DBLP]


  56. Rethinking DRAM design and organization for energy-constrained multi-cores. [Citation Graph (, )][DBLP]


  57. System implications of integrated photonics. [Citation Graph (, )][DBLP]


  58. Emerging technologies and their impact on system design. [Citation Graph (, )][DBLP]


  59. Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. [Citation Graph (, )][DBLP]


  60. McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. [Citation Graph (, )][DBLP]


  61. Implementing high availability memory with a duplication cache. [Citation Graph (, )][DBLP]


  62. High-performance ethernet-based communications for future multi-core processors. [Citation Graph (, )][DBLP]


  63. Future scaling of processor-memory interfaces. [Citation Graph (, )][DBLP]


  64. Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. [Citation Graph (, )][DBLP]


  65. Technical perspective - Software and hardware support for deterministic replay of parallel programs. [Citation Graph (, )][DBLP]


  66. Isolation in Commodity Multicore Processors. [Citation Graph (, )][DBLP]


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