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Jaejin Lee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jaejin Lee, David A. Padua
    Hiding Relaxed Memory Consistency with Compilers. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:111-122 [Conf]
  2. Bernhard Egger, Chihun Kim, Choonki Jang, Yoonsung Nam, Jaejin Lee, Sang Lyul Min
    A dynamic code placement technique for scratchpad memory using postpass optimization. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:223-233 [Conf]
  3. Chanik Park, Junghee Lim, Kiwon Kwon, Jaejin Lee, Sang Lyul Min
    Compiler-assisted demand paging for embedded systems with flash memory. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2004, pp:114-124 [Conf]
  4. Bernhard Egger, Jaejin Lee, Heonshik Shin
    Scratchpad memory management for portable systems with a memory management unit. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2006, pp:321-330 [Conf]
  5. Hyun Yoe, Jaejin Lee
    Design of VDSL Networks for the High Speed Internet Services. [Citation Graph (0, 0)][DBLP]
    GCC (2), 2003, pp:442-445 [Conf]
  6. Mazen Kharbutli, Keith Irwin, Yan Solihin, Jaejin Lee
    Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:288-299 [Conf]
  7. Jaejin Lee, Yan Solihin, Josep Torrellas
    Automatically Mapping Code on an Intelligent Memory Architecture. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:121-0 [Conf]
  8. Jun Lee, Hyuntae Kim, Jaejin Lee
    Information extraction method without original image using turbo code. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2001, pp:880-883 [Conf]
  9. Jaejin Lee, Chee Sun Won
    Image Integrity and Correction using Parities of Error Control Coding. [Citation Graph (0, 0)][DBLP]
    IEEE International Conference on Multimedia and Expo (III), 2000, pp:1297-1300 [Conf]
  10. William Blume, Rudolf Eigenmann, Keith Faigin, John Grout, Jaejin Lee, Thomas Lawrence, Jay Hoeflinger, David A. Padua, Yunheung Paek, Paul Petersen, William M. Pottenger, Lawrence Rauchwerger, Peng Tu, Stephen Weatherford
    Restructuring Programs for High-Speed Computers with Polaris. [Citation Graph (0, 0)][DBLP]
    ICPP Workshop, 1996, pp:149-161 [Conf]
  11. Xing Fang, Jaejin Lee, Samuel P. Midkiff
    Automatic fence insertion for shared memory multiprocessing. [Citation Graph (0, 0)][DBLP]
    ICS, 2003, pp:285-294 [Conf]
  12. Yan Solihin, Jaejin Lee, Josep Torrellas
    Adaptively Mapping Code in an Intelligent Memory Architecture. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:71-84 [Conf]
  13. Changhee Jung, Daeseob Lim, Jaejin Lee, Yan Solihin
    Helper thread prefetching for loosely-coupled multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  14. Yan Solihin, Josep Torrellas, Jaejin Lee
    Using a User-Level Memory Thread for Correlation Prefetching. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:171-182 [Conf]
  15. Chi-Leung Wong, Zehra Sura, David A. Padua, Xing Fang, Jaejin Lee, Samuel P. Midkiff
    The Pensieve Project: A Compiler Infrastructure for Memory Models. [Citation Graph (0, 0)][DBLP]
    ISPAN, 2002, pp:239-244 [Conf]
  16. Jaejin Lee, H. D. K. Moonesinghe
    Adaptively Increasing Performance and Scalability of Automatically Parallelized Programs. [Citation Graph (0, 0)][DBLP]
    LCPC, 2002, pp:203-217 [Conf]
  17. Jaejin Lee, Samuel P. Midkiff, David A. Padua
    Concurrent Static Single Assignment Form and Constant Propagation for Explicitly Parallel Programs. [Citation Graph (0, 0)][DBLP]
    LCPC, 1997, pp:114-130 [Conf]
  18. Zehra Sura, Chi-Leung Wong, Xing Fang, Jaejin Lee, Samuel P. Midkiff, David A. Padua
    Automatic Implementation of Programming Language Consistency Models. [Citation Graph (0, 0)][DBLP]
    LCPC, 2002, pp:172-187 [Conf]
  19. Ji Zhang, Jaejin Lee, Philip K. McKinley
    Optimizing the Java Piped I/O Stream Library for Performance. [Citation Graph (0, 0)][DBLP]
    LCPC, 2002, pp:233-248 [Conf]
  20. Chi-Leung Wong, Zehra Sura, Xing Fang, Kyungwoo Lee, Samuel P. Midkiff, Jaejin Lee, David A. Padua
    Evaluating the Impact of Thread Escape Analysis on a Memory Consistency Model-Aware Compiler. [Citation Graph (0, 0)][DBLP]
    LCPC, 2005, pp:170-184 [Conf]
  21. Changhee Jung, Daeseob Lim, Jaejin Lee, Sangyong Han
    Adaptive execution techniques for SMT multiprocessor architectures. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2005, pp:236-246 [Conf]
  22. Jaejin Lee, David A. Padua, Samuel P. Midkiff
    Basic Compiler Algorithms for Parallel Programs. [Citation Graph (0, 0)][DBLP]
    PPOPP, 1999, pp:1-12 [Conf]
  23. Zehra Sura, Xing Fang, Chi-Leung Wong, Samuel P. Midkiff, Jaejin Lee, David A. Padua
    Compiler techniques for high performance sequentially consistent java programs. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2005, pp:2-13 [Conf]
  24. Sheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, Jack W. Davidson
    Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:33-48 [Conf]
  25. Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
    A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:244-258 [Conf]
  26. Zohar Manna, Nikolaj Bjørner, Anca Browne, Edward Y. Chang, Michael Colón, Luca de Alfaro, Harish Devarajan, Arjun Kapur, Jaejin Lee, Henny Sipma, Tomás E. Uribe
    STeP: The Stanford Temporal Prover. [Citation Graph (0, 0)][DBLP]
    TAPSOFT, 1995, pp:793-794 [Conf]
  27. Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
    A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors. [Citation Graph (0, 0)][DBLP]
    WCET, 2003, pp:91-94 [Conf]
  28. William Blume, Ramon Doallo, Rudolf Eigenmann, John Grout, Jay Hoeflinger, Thomas Lawrence, Jaejin Lee, David A. Padua, Yunheung Paek, William M. Pottenger, Lawrence Rauchwerger, Peng Tu
    Parallel Programming with Polaris. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1996, v:29, n:12, pp:87-81 [Journal]
  29. Samuel P. Midkiff, Jaejin Lee, David A. Padua
    A compiler for multiple memory models. [Citation Graph (0, 0)][DBLP]
    Concurrency and Computation: Practice and Experience, 2004, v:16, n:2-3, pp:197-220 [Journal]
  30. Dug Hun Hong, Jaejin Lee
    A convergence of geometric mean for T-related fuzzy numbers. [Citation Graph (0, 0)][DBLP]
    Fuzzy Sets and Systems, 2001, v:121, n:3, pp:537-543 [Journal]
  31. Jaejin Lee, Samuel P. Midkiff, David A. Padua
    A Constant Propagation Algorithm for Explicitly Parallel Programs. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:5, pp:563-589 [Journal]
  32. Bruce E. Sagan, Jaejin Lee
    An algorithmic sign-reversing involution for special rim-hook tableaux. [Citation Graph (0, 0)][DBLP]
    J. Algorithms, 2006, v:59, n:2, pp:149-161 [Journal]
  33. Mazen Kharbutli, Yan Solihin, Jaejin Lee
    Eliminating Conflict Misses Using Prime Number-Based Cache Indexing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:5, pp:573-586 [Journal]
  34. Jaejin Lee, David A. Padua
    Hiding Relaxed Memory Consistency with a Compiler. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:8, pp:824-833 [Journal]
  35. Yan Solihin, Jaejin Lee, Josep Torrellas
    Automatic Code Mapping on an Intelligent Memory Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1248-1266 [Journal]
  36. Yan Solihin, Jaejin Lee, Josep Torrellas
    Correlation Prefetching with a User-Level Memory Thread. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:6, pp:563-580 [Journal]
  37. Hyungmin Cho, Bernhard Egger, Jaejin Lee, Heonshik Shin
    Dynamic data scratchpad memory management for a memory subsystem with an MMU. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:195-206 [Conf]
  38. Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
    Selective code transformation for dual instruction set processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:2, pp:- [Journal]

  39. COMIC: a coherent shared memory interface for cell be. [Citation Graph (, )][DBLP]


  40. Scratchpad memory management in a multitasking environment. [Citation Graph (, )][DBLP]


  41. Design and implementation of software-managed caches for multicores with local memory. [Citation Graph (, )][DBLP]


  42. FaCSim: a fast and cycle-accurate architecture simulator for embedded systems. [Citation Graph (, )][DBLP]


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