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Publications of Author

1. Per Bjesse
   Automatic Verification of Combinatorial and Pipelined FFT. [Citation Graph (0, 0)][DBLP]
   CAV, 1999, pp:380-393 [Conf]
   
2. Per Bjesse, Tim Leonard, Abdel Mokkedem
   Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers. [Citation Graph (0, 0)][DBLP]
   CAV, 2001, pp:454-464 [Conf]
   
3. Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna
   A proof engine approach to solving combinational design automation problems. [Citation Graph (0, 0)][DBLP]
   DAC, 2002, pp:725-730 [Conf]
   
4. Per Bjesse, James H. Kukula
   Using Counter Example Guided Abstraction Refinement to Find Complex Bugs. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:156-161 [Conf]
   
5. Per Bjesse, Koen Claessen
   SAT-Based Verification without State Space Traversal. [Citation Graph (0, 0)][DBLP]
   FMCAD, 2000, pp:372-389 [Conf]
   
6. Per Bjesse, Arne Borälv
   DAG-aware circuit compression for formal verification. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2004, pp:42-49 [Conf]
   
7. Per Bjesse, James H. Kukula
   Automatic generalized phase abstraction for formal verification. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:1076-1082 [Conf]
   
8. Per Bjesse, Koen Claessen, Mary Sheeran, Satnam Singh
   Lava: Hardware Design in Haskell. [Citation Graph (0, 0)][DBLP]
   ICFP, 1998, pp:174-184 [Conf]
   
9. Per Bjesse, James H. Kukula, Robert F. Damiano, Ted Stanion, Yunshan Zhu
   Guiding SAT Diagnosis with Tree Decompositions. [Citation Graph (0, 0)][DBLP]
   SAT, 2003, pp:315-329 [Conf]
   
10. Per Bjesse
    Industrial Model Checking Based on Satisfiability Solvers. [Citation Graph (0, 0)][DBLP]
    SPIN, 2002, pp:240- [Conf]
    
11. Parosh Aziz Abdulla, Per Bjesse, Niklas Eén
    Symbolic Reachability Analysis Based on SAT-Solvers. [Citation Graph (0, 0)][DBLP]
    TACAS, 2000, pp:411-425 [Conf]
    
12. Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna
    Design automation with mixtures of proof strategies for propositional logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1042-1048 [Journal]
    
13. In-Ho Moon, Per Bjesse, Carl Pixley
    A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1170-1175 [Conf]
    
14. 
    A Practical Approach to Word Level Model Checking of Industrial Netlists. [Citation Graph (, )][DBLP]
    
    
15. 
    Word-Level Sequential Memory Abstraction for Model Checking. [Citation Graph (, )][DBLP]