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Title:
Author:
Narayanan Vijaykrishnan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam
    Leakage Energy Management in Cache Hierarchies. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:131-140 [Conf]
  2. Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Reliability-Aware Co-Synthesis for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:41-50 [Conf]
  3. Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Object duplication for improving reliability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:140-145 [Conf]
  4. Victor M. DeLaLuz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, Ibrahim Kolcu
    Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:288-296 [Conf]
  5. David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin
    Evaluating Run-Time Techniques for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:31-38 [Conf]
  6. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
    Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1200-1203 [Conf]
  7. Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan
    Leakage control in FPGA routing fabric. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:661-664 [Conf]
  8. Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Designing reliable circuit in the presence of soft errors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1- [Conf]
  9. Shengqi Yang, Wayne Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie
    Low-leakage robust SRAM cell design for sub-100nm technologies. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:539-544 [Conf]
  10. Tao Li, Lizy Kurian John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Juan Rubio
    Understanding and improving operating system effects in control flow prediction. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:68-80 [Conf]
  11. Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Energy-oriented compiler optimizations for partitioned memory architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:138-147 [Conf]
  12. Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Energy-efficient instruction cache using page-based placement. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:229-237 [Conf]
  13. Guangyu Chen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mario Wolczko
    Tracking object life cycle for leakage energy optimization. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:213-218 [Conf]
  14. Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf
    Energy savings through compression in embedded Java environments. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:163-168 [Conf]
  15. Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin
    Analyzing heap error behavior in embedded JVM environments. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:230-235 [Conf]
  16. Ananth Hegde, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    VL-CDRAM: variable line sized cached DRAMs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:132-137 [Conf]
  17. Narayanan Vijaykrishnan, N. Ranganathan
    Tuning Branch Predictors to Support Virtual Method Invocation in Java. [Citation Graph (0, 0)][DBLP]
    COOTS, 1999, pp:217-228 [Conf]
  18. Victor Delaluz, Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Scheduler-based DRAM energy management. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:697-702 [Conf]
  19. Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin
    Exploring technology alternatives for nano-scale FPGA interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:921-926 [Conf]
  20. Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh
    Dynamic Management of Scratch-Pad Memory Space. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:690-695 [Conf]
  21. Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye
    Influence of compiler optimizations on system power. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:304-307 [Conf]
  22. Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das
    A low latency router supporting adaptivity for on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:559-564 [Conf]
  23. Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari
    FLAW: FPGA lifetime awareness. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:630-635 [Conf]
  24. Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    Implications of technology scaling on leakage reduction techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:187-190 [Conf]
  25. Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    The design and use of simplepower: a cycle-accurate energy estimation tool. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:340-345 [Conf]
  26. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    A Complete Phase-Locked Loop Power Consumption Model. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1108- [Conf]
  27. Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Compiler-Directed Instruction Duplication for Soft Error Detection. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1056-1057 [Conf]
  28. Jie S. Hu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Power-Efficient Trace Caches. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1091- [Conf]
  29. Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin
    Scheduling Reusable Instructions for Power Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:148-155 [Conf]
  30. Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Thermal-Aware Task Allocation and Scheduling for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:898-899 [Conf]
  31. Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam
    EAC: A Compiler Framework for High-Level Energy Estimation and Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:436-442 [Conf]
  32. Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    A Crosstalk Aware Interconnect with Variable Cycle Transmission. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:102-107 [Conf]
  33. Greg M. Link, Narayanan Vijaykrishnan
    Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:648-649 [Conf]
  34. Andrew J. Ricketts, Kevin M. Irick, Narayanan Vijaykrishnan, Mary Jane Irwin
    Priority scheduling in digital microfluidics-based biochips. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:329-334 [Conf]
  35. Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, R. R. Brooks, Soontae Kim, Wei Zhang 0002
    Masking the Energy Behavior of DES Encryption. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10084-10089 [Conf]
  36. Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan
    Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:218-223 [Conf]
  37. Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Leakage-Aware Interconnect for On-Chip Network. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:230-231 [Conf]
  38. Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    On-chip bus thermal analysis and optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:850-855 [Conf]
  39. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos, Yuan Xie
    Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:64-69 [Conf]
  40. Wei Zhang 0002, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De
    Compiler Support for Reducing Leakage Energy Consumption. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11146-11147 [Conf]
  41. Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Ismail Kadayif
    CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:41-49 [Conf]
  42. Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Chita R. Das
    Exploring Fault-Tolerant Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    DSN, 2006, pp:93-104 [Conf]
  43. Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gadekarla
    Object-Oriented Architectural Support for a Java Processor. [Citation Graph (0, 0)][DBLP]
    ECOOP, 1998, pp:330-354 [Conf]
  44. Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arif Rahman
    Switch Box Architectures for Three-Dimensional FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:335-336 [Conf]
  45. Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan
    Reducing leakage energy in FPGAs using region-constrained placement. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:51-58 [Conf]
  46. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
    Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:265- [Conf]
  47. Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan
    A Dual-VDD Low Power FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:145-157 [Conf]
  48. Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin
    A comparative study of power efficient SRAM designs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:117-122 [Conf]
  49. Wei Xu, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Design of a nanosensor array architecture. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:298-303 [Conf]
  50. J. Juran, Ali R. Hurson, Narayanan Vijaykrishnan, S. Boonsiriwattanakul
    Data Organization and Retrieval on Parallel Air Channels. [Citation Graph (0, 0)][DBLP]
    HiPC, 2000, pp:501-510 [Conf]
  51. Amisha Parikh, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Energy-Aware Instruction Scheduling. [Citation Graph (0, 0)][DBLP]
    HiPC, 2000, pp:335-344 [Conf]
  52. Sudhanva Gurumurthi, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Tao Li, Lizy Kurian John
    Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:141-150 [Conf]
  53. Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin
    DRAM Energy Management Using Software and Hardware Directed Power Mode Control. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:159-170 [Conf]
  54. Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin
    Exploring Wakeup-Free Instruction Scheduling. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:232-243 [Conf]
  55. Guangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko
    Tuning Garbage Collection in an Embedded Java Environment. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:92-0 [Conf]
  56. Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam
    Architectural Issues in Java Runtime Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:387-398 [Conf]
  57. Frank Ghenassia, Narayanan Vijaykrishnan, Mary Jane Irwin
    Analyzing software influences on substrate noise: an ADC perspective. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:916-922 [Conf]
  58. Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Adapative Error Protection for Energy Efficiency. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:2-7 [Conf]
  59. Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin
    Improving soft-error tolerance of FPGA configuration bits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:107-110 [Conf]
  60. Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan
    Thermal characterization and optimization in platform FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:443-447 [Conf]
  61. Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan
    Reducing dTLB Energy Through Dynamic Resizing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:358-363 [Conf]
  62. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim, G. McFarland
    Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:382-387 [Conf]
  63. Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:430-437 [Conf]
  64. Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwad, John Conner
    Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:689-696 [Conf]
  65. Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    A Framework for Energy Estimation of VLIW Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:40-45 [Conf]
  66. N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar
    A VLSI array architecture with dynamic frequency clocking. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:137-140 [Conf]
  67. Samarjeet Singh Tomar, Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Use of Local Memory for Efficient Java Execution. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:468-476 [Conf]
  68. Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    Three-Dimensional Cache Design Exploration Using 3DCacti. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:519-524 [Conf]
  69. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan
    Search speed and power driven integrated software and hardware optimizations for motion estimation algorithms. [Citation Graph (0, 0)][DBLP]
    ICME, 2004, pp:707-710 [Conf]
  70. Tao Li, Lizy Kurian John, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Jyotsna Sabarinathan, Anupama Murthy
    Using complete system simulation to characterize SPECjvm98 benchmarks. [Citation Graph (0, 0)][DBLP]
    ICS, 2000, pp:22-33 [Conf]
  71. R. Athavale, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Influence of Array Allocation Mechanisms on Memory System Energy. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:3- [Conf]
  72. Guilin Chen, Byung-Tae Kang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli
    Energy-Aware Compilation and Execution in Java-Enabled Mobile Devices. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:34- [Conf]
  73. Sudhanva Gurumurthi, Ning An, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Energy and Performance Considerations in Work Partitioning for Mobile Spatial Queries. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:33- [Conf]
  74. Emanuele Lattanzi, Aman Gayasen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Luca Benini, Alessandro Bogliolo
    Improving Java Performance Using Dynamic Method Migration on FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  75. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
    Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  76. Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Designing Energy-Efficient Software. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  77. E. J. Swankoski, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    A Parallel Architecture for Secure FPGA Symmetric Encryption. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  78. Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir
    Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:130-141 [Conf]
  79. Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye
    Energy-driven integrated hardware-software optimizations using SimplePower. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:95-106 [Conf]
  80. G. Esakkimuthu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Memory system energy (poster session): influence of hardware-software optimizations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:244-246 [Conf]
  81. Jie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir
    Exploiting program hotspots and code sequentiality for instruction cache leakage management. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:402-407 [Conf]
  82. Lin Li, Vijay Degalahal, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Soft error and energy consumption interactions: a data cache perspective. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:132-137 [Conf]
  83. Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin, Lizy Kurian John
    On load latency in low-power caches. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:258-261 [Conf]
  84. Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Erik Brockmeyer, Francky Catthoor, Mary Jane Irwin
    Estimating influence of data layout optimizations on SDRAM energy consumption. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:40-43 [Conf]
  85. Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, E. Geethanjali
    Power-aware partitioned cache architectures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:64-67 [Conf]
  86. Eun Jung Kim, Ki Hwan Yum, Greg M. Link, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mazin S. Yousif, Chita R. Das
    Energy optimization techniques in cluster interconnects. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:459-464 [Conf]
  87. Sudhanva Gurumurthi, Jianyong Zhang, Anand Sivasubramaniam, Mahmut T. Kandemir, Hubertus Franke, Narayanan Vijaykrishnan, Mary Jane Irwin
    Interplay of energy and performance for disk arrays running transaction processing workloads. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2003, pp:123-132 [Conf]
  88. Vijay Degalahal, R. Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    The Effect of Threshold Voltages on the Soft Error Rate. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:503-508 [Conf]
  89. Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:98-104 [Conf]
  90. Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Charles Addo-Quaye, Theo Theocharides, Mary Jane Irwin
    Thermal-Aware Floorplanning Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:634-639 [Conf]
  91. I.-C. Lin, S. Srinivasan, Narayanan Vijaykrishnan, N. Dhanwada
    Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:775-780 [Conf]
  92. Greg M. Link, Narayanan Vijaykrishnan
    Thermal Trends in Emerging Technologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:625-632 [Conf]
  93. Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Variation Analysis of CAM Cells. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:333-338 [Conf]
  94. K. Ramakrishnan, R. Rajaraman, S. Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Variation Impact on SER of Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:911-916 [Conf]
  95. Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud
    Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:67-72 [Conf]
  96. Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir
    Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:127-132 [Conf]
  97. Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Hardware-Software Co-Adaptation for Data-Intensive Embedded Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:20-25 [Conf]
  98. J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
    High Performance Array Processor for Video Decoding. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:28-33 [Conf]
  99. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    Impact of Technology Scaling in the Clock System Power. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:59-64 [Conf]
  100. M. Pirretti, Greg M. Link, R. R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Fault Tolerant Algorithms for Network-On-Chip Interconnect. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:46-51 [Conf]
  101. Hendra Saputra, Ozcan Ozturk, Narayanan Vijaykrishnan, Mahmut T. Kandemir, R. R. Brooks
    A Data-Driven Approach for Embedded Security. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:104-109 [Conf]
  102. Theo Theocharides, Greg M. Link, E. J. Swankoski, Narayanan Vijaykrishnan, Mary Jane Irwin, Herman Schmit
    Evaluating Alternative Implementations for LDPC Decoder Check Node Function. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:77-82 [Conf]
  103. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie
    Reliability-Aware SOC Voltage Islands Partition and Floorplan. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:343-348 [Conf]
  104. Suresh Srinivasan, Narayanan Vijaykrishnan
    Variation Aware Placement for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:422-423 [Conf]
  105. Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie
    Delay and Energy Efficient Data Transmission for On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:355-360 [Conf]
  106. Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin
    A Parallel Architecture for Hardware Face Detection. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:452-453 [Conf]
  107. Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin
    Investigating Simple Low Latency Reliable Multiported Register Files. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:375-382 [Conf]
  108. Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud
    Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:516-517 [Conf]
  109. Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Field level analysis for heap space optimization in embedded java environments. [Citation Graph (0, 0)][DBLP]
    ISMM, 2004, pp:131-142 [Conf]
  110. Narayanan Vijaykrishnan, Mahmut T. Kandemir, Soontae Kim, Samarjeet Singh Tomar, Anand Sivasubramaniam, Mary Jane Irwin
    Energy Behavior of Java Applications from the Memory Perspective. [Citation Graph (0, 0)][DBLP]
    Java™ Virtual Machine Research and Technology Symposium, 2001, pp:207-220 [Conf]
  111. Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko
    Adaptive Garbage Collection for Battery-Operated Environments. [Citation Graph (0, 0)][DBLP]
    Java™ Virtual Machine Research and Technology Symposium, 2002, pp:1-12 [Conf]
  112. Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim
    Experimental Evaluation of Energy Behavior of Iteration Space Tiling. [Citation Graph (0, 0)][DBLP]
    LCPC, 2000, pp:142-157 [Conf]
  113. Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Compiler-directed thermal management for VLIW functional units. [Citation Graph (0, 0)][DBLP]
    LCTES, 2006, pp:163-172 [Conf]
  114. Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hendra Saputra, Wei Zhang 0002
    Compiler-directed cache polymorphism. [Citation Graph (0, 0)][DBLP]
    LCTES-SCOPES, 2002, pp:165-174 [Conf]
  115. Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, J. Ramanujam
    Morphable Cache Architectures: Potential Benefits. [Citation Graph (0, 0)][DBLP]
    LCTES/OM, 2001, pp:128-137 [Conf]
  116. Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim
    Towards Energy-Aware Iteration Space Tiling. [Citation Graph (0, 0)][DBLP]
    LCTES, 2000, pp:211-215 [Conf]
  117. Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Adapting instruction level parallelism for optimizing leakage in VLIW architectures. [Citation Graph (0, 0)][DBLP]
    LCTES, 2003, pp:275-283 [Conf]
  118. Hendra Saputra, Guangyu Chen, R. R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Code protection for resource-constrained embedded devices. [Citation Graph (0, 0)][DBLP]
    LCTES, 2004, pp:240-248 [Conf]
  119. Hendra Saputra, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Jie S. Hu, Chung-Hsing Hsu, Ulrich Kremer
    Energy-conscious compilation based on voltage scaling. [Citation Graph (0, 0)][DBLP]
    LCTES-SCOPES, 2002, pp:2-11 [Conf]
  120. Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Compiler-directed instruction cache leakage optimization. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:208-218 [Conf]
  121. Wei Zhang 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai
    Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:102-113 [Conf]
  122. Chrysostomos Nicopoulos, Dongkook Park, Jongman Kim, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
    ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:333-346 [Conf]
  123. Pradeep K. Khosla, Herman Schmit, Mary Jane Irwin, Narayanan Vijaykrishnan, Tom Cain, Steven P. Levitan, Dave Landis
    SoC Design Skills: Collaboration Builds a Stronger SoC Design Team. [Citation Graph (0, 0)][DBLP]
    MSE, 2001, pp:42-43 [Conf]
  124. Herman Schmit, Thomas Kroll, Max Khusid, Ivan S. Kourtev, Narayanan Vijaykrishnan, David L. Landis
    The Sandbox Design Experience Course. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:39-40 [Conf]
  125. Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Bernd Mathiske, Mario Wolczko
    Heap compression for memory-constrained Java environments. [Citation Graph (0, 0)][DBLP]
    OOPSLA, 2003, pp:282-301 [Conf]
  126. Ismail Kadayif, T. Chinoda, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam
    vEC: virtual energy counters. [Citation Graph (0, 0)][DBLP]
    PASTE, 2001, pp:28-31 [Conf]
  127. Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam
    A Holistic Approach to System Level Energy Optimization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:88-107 [Conf]
  128. Ning An, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Sudhanva Gurumurthi
    Analyzing energy behavior of spatial access methods for memory-resident data. [Citation Graph (0, 0)][DBLP]
    VLDB, 2001, pp:411-420 [Conf]
  129. Narayanan Vijaykrishnan
    Energy Efficient and Reliable System Design. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:6-9 [Conf]
  130. M. DeRenzo, Mary Jane Irwin, Narayanan Vijaykrishnan
    Designing Leakage Aware Multipliers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:654-657 [Conf]
  131. Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin
    Analyzing Soft Errors in Leakage Optimized SRAM Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:227-233 [Conf]
  132. Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, Ibrahim Kolcu
    Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:288-0 [Conf]
  133. David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin
    Evaluating Run-Time Techniques for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:31-38 [Conf]
  134. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir
    Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:248-253 [Conf]
  135. Kevin M. Irick, Wei Xu, Narayanan Vijaykrishnan, Mary Jane Irwin
    A Nanosensor Array-Based VLSI Gas Discriminator. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:241-246 [Conf]
  136. Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan
    Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:440-0 [Conf]
  137. J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf
    An Architecture for Motion Estimation in the Transform Domain. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:1077-1082 [Conf]
  138. R. Rajaraman, J. S. Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:499-502 [Conf]
  139. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
    Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:736-741 [Conf]
  140. Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal
    A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:657-664 [Conf]
  141. Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:374-379 [Conf]
  142. Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin
    Implementing LDPC Decoding on Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:134-137 [Conf]
  143. Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf
    Embedded Hardware Face Detection. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:133-0 [Conf]
  144. Narayanan Vijaykrishnan, N. Ranganathan
    SUBGEN: a genetic approach for subcircuit extraction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:343-345 [Conf]
  145. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang
    Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:165-170 [Conf]
  146. K. Ramakrishnan, S. Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin
    Impact of NBTI on FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:717-722 [Conf]
  147. Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    Architecting Microprocessor Components in 3D Design Space. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:103-108 [Conf]
  148. Jongman Kim, Dongkook Park, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Chita R. Das
    Design and analysis of an NoC architecture from performance, reliability and energy perspective. [Citation Graph (0, 0)][DBLP]
    ANCS, 2005, pp:173-182 [Conf]
  149. Theocharis Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin
    Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip. [Citation Graph (0, 0)][DBLP]
    Advances in Computers, 2005, v:63, n:, pp:36-92 [Journal]
  150. Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan
    Leakage Current: Moore's Law Meets Static Power. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:12, pp:68-75 [Journal]
  151. Narayanan Vijaykrishnan, Yuan Xie
    Reliability Concerns in Embedded System Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2006, v:39, n:1, pp:118-120 [Journal]
  152. Srinivasan Murali, Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli
    Analysis of Error Recovery Schemes for Networks on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:434-442 [Journal]
  153. Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf
    Using Memory Compression for Energy Reduction in an Embedded Java System. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:5, pp:537-556 [Journal]
  154. Mary Jane Irwin, Narayanan Vijaykrishnan
    Editorial. [Citation Graph (0, 0)][DBLP]
    JETC, 2005, v:1, n:1, pp:1-6 [Journal]
  155. Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam
    Managing Leakage Energy in Cache Hierarchies. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2003, v:5, n:, pp:- [Journal]
  156. Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    An integer linear programming-based tool for wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2005, v:65, n:3, pp:247-260 [Journal]
  157. Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Reducing instruction cache energy consumption using a compiler-based strategy. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:1, pp:3-33 [Journal]
  158. Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin
    Hardware and Software Techniques for Controlling DRAM Power Modes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1154-1173 [Journal]
  159. Eun Jung Kim, Greg M. Link, Ki Hwan Yum, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Chita R. Das
    A Holistic Approach to Designing Energy-Efficient Cluster Interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:6, pp:660-671 [Journal]
  160. Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam, Juan Rubio, Jyotsna Sabarinathan
    Java Runtime Systems: Characterization and Architectural Implications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:2, pp:131-146 [Journal]
  161. Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye, David Duarte
    Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:1, pp:59-76 [Journal]
  162. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan
    Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:6, pp:714-726 [Journal]
  163. Tao Li, Lizy Kurian John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Juan Rubio
    OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:1, pp:2-17 [Journal]
  164. Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh
    A compiler-based approach for dynamically managing scratch-pad memories in embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:243-260 [Journal]
  165. Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
    Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:5, pp:655-662 [Journal]
  166. Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf
    An efficient architecture for motion estimation and compensation in the transform domain. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:2, pp:191-201 [Journal]
  167. Guangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko
    Tuning garbage collection for reducing memory system energy in an embedded java environment. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2002, v:1, n:1, pp:27-55 [Journal]
  168. J. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Analyzing data reuse for cache reconfiguration. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:4, pp:851-876 [Journal]
  169. Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam
    Compiler-directed high-level energy estimation and optimization. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:4, pp:819-850 [Journal]
  170. Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin
    Partitioned instruction cache architecture for energy efficiency. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:2, pp:163-185 [Journal]
  171. Wei Zhang 0002, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Reducing dynamic and leakage energy in VLIW architectures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:1-28 [Journal]
  172. Guangyu Chen, Byung-Tae Kang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli
    Studying Energy Trade Offs in Offloading Computation/Compilation in Java-Enabled Mobile Devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:9, pp:795-809 [Journal]
  173. Vijay Degalahal, Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Soft errors issues in low-power caches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1157-1166 [Journal]
  174. Christian Piguet, Narayanan Vijaykrishnan
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:129-130 [Journal]
  175. Christian Piguet, Narayanan Vijaykrishnan
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:233-234 [Journal]
  176. Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    Characterization and modeling of run-time techniques for leakage power reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1221-1233 [Journal]
  177. Ning An, Sudhanva Gurumurthi, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Energy-performance trade-offs for spatial access methods on memory-resident data. [Citation Graph (0, 0)][DBLP]
    VLDB J., 2002, v:11, n:3, pp:179-197 [Journal]
  178. J. Juran, Ali R. Hurson, Narayanan Vijaykrishnan, Soontae Kim
    Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues. [Citation Graph (0, 0)][DBLP]
    Wireless Networks, 2004, v:10, n:2, pp:183-195 [Journal]
  179. Madhu Mutyam, Narayanan Vijaykrishnan
    Working with process variation aware caches. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1152-1157 [Conf]
  180. Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud
    Thermally robust clocking schemes for 3D integrated circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1206-1211 [Conf]
  181. Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud
    Assessing carbon nanotube bundle interconnect for future FPGA architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:307-312 [Conf]
  182. Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
    A novel dimensionally-decomposed router for on-chip communication in 3D architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:138-149 [Conf]
  183. W.-L. Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Thermal-Aware Task Allocation and Scheduling for Embedded Systems [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  184. Greg M. Link, Narayanan Vijaykrishnan
    Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  185. Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye
    Influence of compiler optimizations on system power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:801-804 [Journal]
  186. Benjamin Bishop, V. Lyuboslavsky, Narayanan Vijaykrishnan, Mary Jane Irwin
    Design considerations for databus charge recovery. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:104-106 [Journal]
  187. D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    A clock power model to evaluate impact of architectural and technology optimizations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:844-855 [Journal]
  188. Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin
    Reducing non-deterministic loads in low-power caches via early cache set resolution. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:5, pp:293-301 [Journal]

  189. A framework for estimating NBTI degradation of microarchitectural components. [Citation Graph (, )][DBLP]


  190. Exploiting clock skew scheduling for FPGA. [Citation Graph (, )][DBLP]


  191. A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching. [Citation Graph (, )][DBLP]


  192. Investigating the impact of NBTI on different power saving cache strategies. [Citation Graph (, )][DBLP]


  193. Analysis and solutions to issue queue process variation. [Citation Graph (, )][DBLP]


  194. Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. [Citation Graph (, )][DBLP]


  195. Variation-aware task allocation and scheduling for MPSoC. [Citation Graph (, )][DBLP]


  196. FPGA routing architecture analysis under variations. [Citation Graph (, )][DBLP]


  197. Comparative analysis of NBTI effects on low power and high performance flip-flops. [Citation Graph (, )][DBLP]


  198. MIRA: A Multi-layered On-Chip Interconnect Router Architecture. [Citation Graph (, )][DBLP]


  199. Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures. [Citation Graph (, )][DBLP]


  200. Hierarchical Soft Error Estimation Tool (HSEET). [Citation Graph (, )][DBLP]


  201. A case for dynamic frequency tuning in on-chip networks. [Citation Graph (, )][DBLP]


  202. Leakage Optimized DECAP Design for FPGAs. [Citation Graph (, )][DBLP]


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