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Author:
Mary Jane Irwin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam
    Leakage Energy Management in Cache Hierarchies. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:131-140 [Conf]
  2. Mary Jane Irwin
    Reconfigurable Pipeline Systems. [Citation Graph (0, 0)][DBLP]
    ACM Annual Conference (1), 1978, pp:86-92 [Conf]
  3. Robert Michael Owens, Raminder Singh Bajwa, Mary Jane Irwin
    Reducing the number of counters needed for integer multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1995, pp:38-41 [Conf]
  4. Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens, Amulya K. Garga
    Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:65-71 [Conf]
  5. Kevin P. Acken, Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens
    An Architectural Design For Parallel Fractal Compression. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:3-11 [Conf]
  6. Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
    The MGAP's programming environment and the *C++ language. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:121-124 [Conf]
  7. Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens
    Motion Estimation Algorithms on Fine Grain Array Processor. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:204-213 [Conf]
  8. Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Reliability-Aware Co-Synthesis for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:41-50 [Conf]
  9. G. Chen, Mahmut T. Kandemir, Mary Jane Irwin, Gokhan Memik
    Compiler-directed selective data protection against soft errors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:713-716 [Conf]
  10. Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Object duplication for improving reliability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:140-145 [Conf]
  11. Victor M. DeLaLuz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, Ibrahim Kolcu
    Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:288-296 [Conf]
  12. David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin
    Evaluating Run-Time Techniques for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:31-38 [Conf]
  13. Ozcan Ozturk, Mahmut T. Kandemir, G. Chen, Mary Jane Irwin, Mustafa Karaköy
    Customized on-chip memories for embedded chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:743-748 [Conf]
  14. Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Designing reliable circuit in the presence of soft errors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1- [Conf]
  15. Feihui Li, Guangyu Chen, Mahmut T. Kandemir, Mary Jane Irwin
    Compiler-directed proactive power management for networks. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:137-146 [Conf]
  16. Guilin Chen, Mahmut T. Kandemir, Hendra Saputra, Mary Jane Irwin
    Exploiting bank locality in multi-bank memories. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:287-297 [Conf]
  17. Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Energy-oriented compiler optimizations for partitioned memory architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:138-147 [Conf]
  18. Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Energy-efficient instruction cache using page-based placement. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:229-237 [Conf]
  19. Wei Zhang 0002, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin
    Performance, energy, and reliability tradeoffs in replicating hot cache lines. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:309-317 [Conf]
  20. Mahmut T. Kandemir, Mary Jane Irwin, Guilin Chen, J. Ramanujam
    Address Register Assignment for Reducing Code Size. [Citation Graph (0, 0)][DBLP]
    CC, 2003, pp:273-289 [Conf]
  21. Guangyu Chen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mario Wolczko
    Tracking object life cycle for leakage energy optimization. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:213-218 [Conf]
  22. Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf
    Energy savings through compression in embedded Java environments. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:163-168 [Conf]
  23. Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin
    Analyzing heap error behavior in embedded JVM environments. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:230-235 [Conf]
  24. Ananth Hegde, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    VL-CDRAM: variable line sized cached DRAMs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:132-137 [Conf]
  25. Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin
    Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:87-92 [Conf]
  26. J. A. Beekman, Robert Michael Owens, Mary Jane Irwin
    Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:357-362 [Conf]
  27. Rita Yu Chen, Robert Michael Owens, Mary Jane Irwin, Raminder Singh Bajwa
    Validation of an Architectural Level Power Analysis Technique. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:242-245 [Conf]
  28. Victor Delaluz, Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Scheduler-based DRAM energy management. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:697-702 [Conf]
  29. Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin
    Exploring technology alternatives for nano-scale FPGA interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:921-926 [Conf]
  30. Pao-Po Hou, Robert Michael Owens, Mary Jane Irwin
    DECOMPOSER: A Synthesizer for Systolic Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:650-653 [Conf]
  31. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
    Multi-Level Logic Synthesis Using Communication Complexity. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:215-220 [Conf]
  32. Mary Jane Irwin, Robert Michael Owens
    A Comparison of Four Two-dimensional Gate Matrix Layout Tools. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:698-701 [Conf]
  33. Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh
    Dynamic Management of Scratch-Pad Memory Space. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:690-695 [Conf]
  34. Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye
    Influence of compiler optimizations on system power. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:304-307 [Conf]
  35. Soohong Kim, Robert Michael Owens, Mary Jane Irwin
    Experiments with a Performance Driven Module Generator. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:687-690 [Conf]
  36. Huzefa Mehta, Manjit Borah, Robert Michael Owens, Mary Jane Irwin
    Accurate Estimation of Combinational Circuit Activity. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:618-622 [Conf]
  37. Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
    Energy Characterization based on Clustering. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:702-707 [Conf]
  38. Robert Michael Owens, Mary Jane Irwin
    An Overview of the Penn State Design System. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:516-522 [Conf]
  39. Ozcan Ozturk, Mahmut T. Kandemir, I. Demirkiran, Guangyu Chen, Mary Jane Irwin
    Data compression for improving SPM behavior. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:401-406 [Conf]
  40. Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    Implications of technology scaling on leakage reduction techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:187-190 [Conf]
  41. Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    The design and use of simplepower: a cycle-accurate energy estimation tool. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:340-345 [Conf]
  42. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    A Complete Phase-Locked Loop Power Consumption Model. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1108- [Conf]
  43. Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Compiler-Directed Instruction Duplication for Soft Error Detection. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1056-1057 [Conf]
  44. Jie S. Hu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Power-Efficient Trace Caches. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1091- [Conf]
  45. Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin
    Scheduling Reusable Instructions for Power Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:148-155 [Conf]
  46. Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Thermal-Aware Task Allocation and Scheduling for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:898-899 [Conf]
  47. Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam
    EAC: A Compiler Framework for High-Level Energy Estimation and Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:436-442 [Conf]
  48. Mahmut T. Kandemir, Guangyu Chen, Feihui Li, Mary Jane Irwin, Ibrahim Kolcu
    Activity clustering for leakage management in SPMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:696-697 [Conf]
  49. Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    A Crosstalk Aware Interconnect with Variable Cycle Transmission. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:102-107 [Conf]
  50. Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin
    BB-GC: Basic-Block Level Garbage Collection. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1032-1037 [Conf]
  51. Andrew J. Ricketts, Kevin M. Irick, Narayanan Vijaykrishnan, Mary Jane Irwin
    Priority scheduling in digital microfluidics-based biochips. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:329-334 [Conf]
  52. Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, R. R. Brooks, Soontae Kim, Wei Zhang 0002
    Masking the Energy Behavior of DES Encryption. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10084-10089 [Conf]
  53. Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Leakage-Aware Interconnect for On-Chip Network. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:230-231 [Conf]
  54. Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    On-chip bus thermal analysis and optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:850-855 [Conf]
  55. Wei Zhang 0002, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De
    Compiler Support for Reducing Leakage Energy Consumption. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11146-11147 [Conf]
  56. Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Ismail Kadayif
    CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:41-49 [Conf]
  57. Mahmut T. Kandemir, Ozcan Ozturk, Mary Jane Irwin, Ibrahim Kolcu
    Using Data Compression to Increase Energy Savings in Multi-bank Memories. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:310-317 [Conf]
  58. Victor De La Luz, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin
    Exploring the Possibility of Operating in the Compressed Domain. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:507-515 [Conf]
  59. Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan
    Reducing leakage energy in FPGAs using region-constrained placement. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:51-58 [Conf]
  60. Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan
    A Dual-VDD Low Power FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:145-157 [Conf]
  61. Kevin P. Acken, Eric Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
    The MGAP Family of Processor Arrays. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:105-0 [Conf]
  62. Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin
    SPARTA: Simulation of Physics on a Real-Time Architecture. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:177-182 [Conf]
  63. Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin
    The Design of a Register Renaming Unit. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:34-37 [Conf]
  64. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
    Fast algorithm for performance-oriented Steiner routing. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:198-203 [Conf]
  65. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
    Recent Developments in Performance Driven Steiner Routing: An Overview. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:137-142 [Conf]
  66. Eric Gayles, Kevin P. Acken, Robert Michael Owens, Mary Jane Irwin
    A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:182-0 [Conf]
  67. Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin
    A comparative study of power efficient SRAM designs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:117-122 [Conf]
  68. Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
    Some Issues in Gray Code Addressing. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:178-181 [Conf]
  69. Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin
    Using data compression in an MPSoC architecture for improving performance. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:353-356 [Conf]
  70. Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Ibrahim Kolcu
    Tuning data replication for improving behavior of MPSoC applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:170-173 [Conf]
  71. Wei Xu, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Design of a nanosensor array architecture. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:298-303 [Conf]
  72. Manjit Borah, Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
    The MGAP: A High Performance, User Programmable, Multifunctional Architecture for DS. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:96-104 [Conf]
  73. Amisha Parikh, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Energy-Aware Instruction Scheduling. [Citation Graph (0, 0)][DBLP]
    HiPC, 2000, pp:335-344 [Conf]
  74. Sudhanva Gurumurthi, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Tao Li, Lizy Kurian John
    Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:141-150 [Conf]
  75. Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin
    DRAM Energy Management Using Software and Hardware Directed Power Mode Control. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:159-170 [Conf]
  76. Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin
    Exploring Wakeup-Free Instruction Scheduling. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:232-243 [Conf]
  77. Guangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko
    Tuning Garbage Collection in an Embedded Java Environment. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:92-0 [Conf]
  78. Sayaka Akioka, Konrad Malkowski, Padma Raghavan, Mary Jane Irwin, Lois C. McInnes, Boyana Norris
    Characterizing the Performance and Energy Attributes of Scientific Simulations. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science (1), 2006, pp:242-249 [Conf]
  79. Frank Ghenassia, Narayanan Vijaykrishnan, Mary Jane Irwin
    Analyzing software influences on substrate noise: an ADC perspective. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:916-922 [Conf]
  80. Mahmut T. Kandemir, Mary Jane Irwin, Guilin Chen, Ibrahim Kolcu
    Banked scratch-pad memory management for reducing leakage energy consumption. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:120-124 [Conf]
  81. Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Adapative Error Protection for Energy Efficiency. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:2-7 [Conf]
  82. Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin
    Improving soft-error tolerance of FPGA configuration bits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:107-110 [Conf]
  83. Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan
    Reducing dTLB Energy Through Dynamic Resizing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:358-363 [Conf]
  84. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim, G. McFarland
    Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:382-387 [Conf]
  85. Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:430-437 [Conf]
  86. Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    A Framework for Energy Estimation of VLIW Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:40-45 [Conf]
  87. Samarjeet Singh Tomar, Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Use of Local Memory for Efficient Java Execution. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:468-476 [Conf]
  88. Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    Three-Dimensional Cache Design Exploration Using 3DCacti. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:519-524 [Conf]
  89. Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin
    Hardware/Software Co-design for Real-Time Physical Modeling. [Citation Graph (0, 0)][DBLP]
    IEEE International Conference on Multimedia and Expo (III), 2000, pp:1363-1366 [Conf]
  90. Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun
    Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPADS (1), 2006, pp:383-390 [Conf]
  91. Tsang-Ling Sheu, Woei Lin, Chita R. Das, Mary Jane Irwin
    Distributed Fault Diagnosis in the Butterfly Parallel Processor. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1989, pp:172-175 [Conf]
  92. R. Athavale, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Influence of Array Allocation Mechanisms on Memory System Energy. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:3- [Conf]
  93. Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
    Image Processing with the MGAP: A Cost Effective Solution. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:439-443 [Conf]
  94. Benjamin Bishop, Robert Michael Owens, Mary Jane Irwin
    Aggressive Dynamic Execution of Multimedia Kernel Traces. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:640-646 [Conf]
  95. Guilin Chen, Byung-Tae Kang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli
    Energy-Aware Compilation and Execution in Java-Enabled Mobile Devices. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:34- [Conf]
  96. Sudhanva Gurumurthi, Ning An, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Energy and Performance Considerations in Work Partitioning for Mobile Spatial Queries. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:33- [Conf]
  97. Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens, Chen-Mi Wu
    Dynamic Space Warping Algorithms on Fine-Graln Array Processors. [Citation Graph (0, 0)][DBLP]
    IPPS, 1994, pp:921-925 [Conf]
  98. Chun Liu, Anand Sivasubramaniam, Mahmut T. Kandemir, Mary Jane Irwin
    Exploiting Barriers to Optimize Power Consumption of CMPs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  99. Padma Raghavan, Mary Jane Irwin, Lois C. McInnes, Boyana Norris
    Adaptive Software for Scientific Computing: Co-Managing Quality-Performance-Power Tradeoffs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  100. Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Designing Energy-Efficient Software. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  101. E. J. Swankoski, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    A Parallel Architecture for Secure FPGA Symmetric Encryption. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  102. Chun Liu, Anand Sivasubramaniam, Mahmut T. Kandemir, Mary Jane Irwin
    Enhancing L2 organization for CMPs with a center cell. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  103. Konrad Malkowski, Ingyu Lee, Padma Raghavan, Mary Jane Irwin
    On improving performance and energy profiles of sparse scientific applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  104. Konrad Malkowski, Ingyu Lee, Padma Raghavan, Mary Jane Irwin
    Conjugate gradient sparse solvers: performance-power characteristics. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  105. Mary Jane Irwin
    A Pipelined Processing Unit for On-Line Division. [Citation Graph (0, 0)][DBLP]
    ISCA, 1978, pp:24-30 [Conf]
  106. Mary Jane Irwin, Don Heller
    Online Pipeline Systems for Recursive Numeric Computations. [Citation Graph (0, 0)][DBLP]
    ISCA, 1980, pp:292-299 [Conf]
  107. Robert Michael Owens, Mary Jane Irwin
    On-Line Algorithms for the Design of Pipeline Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1979, pp:12-19 [Conf]
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    Logic synthesis for field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1280-1287 [Journal]
  210. Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh
    A compiler-based approach for dynamically managing scratch-pad memories in embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:243-260 [Journal]
  211. Robert Michael Owens, Mary Jane Irwin
    A System for Designing, Simulating, and Testing High Performance VLSI Signal Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:420-428 [Journal]
  212. Douglas S. Reeves, Mary Jane Irwin
    Fast Methods for Switch-Level Verification of MOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:766-779 [Journal]
  213. Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
    Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:5, pp:655-662 [Journal]
  214. Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf
    An efficient architecture for motion estimation and compensation in the transform domain. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:2, pp:191-201 [Journal]
  215. Guangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko
    Tuning garbage collection for reducing memory system energy in an embedded java environment. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2002, v:1, n:1, pp:27-55 [Journal]
  216. J. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Analyzing data reuse for cache reconfiguration. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:4, pp:851-876 [Journal]
  217. Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam
    Compiler-directed high-level energy estimation and optimization. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:4, pp:819-850 [Journal]
  218. Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin
    Partitioned instruction cache architecture for energy efficiency. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:2, pp:163-185 [Journal]
  219. Wei Zhang 0002, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Reducing dynamic and leakage energy in VLIW architectures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:1-28 [Journal]
  220. Guilin Chen, Mahmut T. Kandemir, Mary Jane Irwin, J. Ramanujam
    Reducing code size through address register assignment. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:225-258 [Journal]
  221. Rita Yu Chen, Mary Jane Irwin, Raminder Singh Bajwa
    Architecture-level power estimation and design experiments. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:1, pp:50-66 [Journal]
  222. Mary Jane Irwin
    Editorial. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:265-266 [Journal]
  223. Guangyu Chen, Byung-Tae Kang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli
    Studying Energy Trade Offs in Offloading Computation/Compilation in Java-Enabled Mobile Devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:9, pp:795-809 [Journal]
  224. Mahmut T. Kandemir, Mary Jane Irwin, Guangyu Chen, Ibrahim Kolcu
    Compiler-guided leakage optimization for banked scratch-pad memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1136-1146 [Journal]
  225. Vijay Degalahal, Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Soft errors issues in low-power caches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1157-1166 [Journal]
  226. Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    Characterization and modeling of run-time techniques for leakage power reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1221-1233 [Journal]
  227. Ning An, Sudhanva Gurumurthi, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Energy-performance trade-offs for spatial access methods on memory-resident data. [Citation Graph (0, 0)][DBLP]
    VLDB J., 2002, v:11, n:3, pp:179-197 [Journal]
  228. S. Conner, Sayaka Akioka, Mary Jane Irwin, Padma Raghavan
    Link Shutdown Opportunities During Collective Communications in 3-D Torus Nets. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  229. Konrad Malkowski, Padma Raghavan, Mary Jane Irwin
    Memory Optimizations For Fast Power-Aware Sparse Computations. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  230. Konrad Malkowski, Greg M. Link, Padma Raghavan, Mary Jane Irwin
    Load Miss Prediction - Exploiting Power Performance Trade-offs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  231. Ronald F. Boisvert, Mary Jane Irwin, Holly E. Rushmeier
    Evolving the ACM journal distribution program. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 2007, v:50, n:9, pp:19-20 [Journal]
  232. W.-L. Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Thermal-Aware Task Allocation and Scheduling for Embedded Systems [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  233. Yuh-Fang Tsai, Vijaykrishnan Narayaynan, Yuan Xie, Mary Jane Irwin
    Leakage-Aware Interconnect for On-Chip Network [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  234. Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder Singh Bajwa, W.-L. Yang
    The design and implementation of the Arithmetic Cube II, a VLSI signal processing system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:491-502 [Journal]
  235. Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
    Power-delay characteristics of CMOS adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:377-381 [Journal]
  236. Gayles Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
    The design of the MGAP-2: a micro-grained massively parallel array. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:709-716 [Journal]
  237. Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye
    Influence of compiler optimizations on system power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:801-804 [Journal]
  238. Benjamin Bishop, V. Lyuboslavsky, Narayanan Vijaykrishnan, Mary Jane Irwin
    Design considerations for databus charge recovery. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:104-106 [Journal]
  239. D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    A clock power model to evaluate impact of architectural and technology optimizations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:844-855 [Journal]
  240. Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin
    Reducing non-deterministic loads in low-power caches via early cache set resolution. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:5, pp:293-301 [Journal]

  241. Ring Prediction for Non-Uniform Cache Architectures. [Citation Graph (, )][DBLP]


  242. Adaptive set pinning: managing shared caches in chip multiprocessors. [Citation Graph (, )][DBLP]


  243. Analysis and solutions to issue queue process variation. [Citation Graph (, )][DBLP]


  244. A low-power phase change memory based hybrid cache architecture. [Citation Graph (, )][DBLP]


  245. Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors. [Citation Graph (, )][DBLP]


  246. In-Network Caching for Chip Multiprocessors. [Citation Graph (, )][DBLP]


  247. Integrated code and data placement in two-dimensional mesh based chip multiprocessors. [Citation Graph (, )][DBLP]


  248. Ring data location prediction scheme for Non-Uniform Cache Architectures. [Citation Graph (, )][DBLP]


  249. A digit online arithmetic simulator. [Citation Graph (, )][DBLP]


  250. Managing power, performance and reliability trade-offs. [Citation Graph (, )][DBLP]


  251. A helper thread based EDP reduction scheme for adapting application execution in CMPs. [Citation Graph (, )][DBLP]


  252. Evaluating the role of scratchpad memories in chip multiprocessors for sparse matrix computations. [Citation Graph (, )][DBLP]


  253. Shared caches in multicores: the good, the bad, and the ugly. [Citation Graph (, )][DBLP]


  254. Phase-aware adaptive hardware selection for power-efficient scientific computations. [Citation Graph (, )][DBLP]


  255. Hierarchical Soft Error Estimation Tool (HSEET). [Citation Graph (, )][DBLP]


  256. Compiler directed network-on-chip reliability enhancement for chip multiprocessors. [Citation Graph (, )][DBLP]


  257. Cache topology aware computation mapping for multicores. [Citation Graph (, )][DBLP]


  258. A novel migration-based NUCA design for chip multiprocessors. [Citation Graph (, )][DBLP]


  259. Implementation and evaluation of a migration-based NUCA design for chip multiprocessors. [Citation Graph (, )][DBLP]


  260. Arithmetic unit design using 180nm TSV-based 3D stacking technology. [Citation Graph (, )][DBLP]


  261. Technology scaling redirects main memories: technical perspective. [Citation Graph (, )][DBLP]


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