The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Serdar Tasiran: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rajeev Alur, Thomas A. Henzinger, Freddy Y. C. Mang, Shaz Qadeer, Sriram K. Rajamani, Serdar Tasiran
    MOCHA: Modularity in Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 1998, pp:521-525 [Conf]
  2. Serdar Tasiran, Robert K. Brayton
    STARI: A Case Study in Compositional and Hierarchical Timing Verification. [Citation Graph (0, 0)][DBLP]
    CAV, 1997, pp:191-201 [Conf]
  3. Serdar Tasiran, Ramin Hojati, Robert K. Brayton
    Language containment of non-deterministic omega-automata. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:261-277 [Conf]
  4. Serdar Tasiran, Rajeev Alur, Robert P. Kurshan, Robert K. Brayton
    Verifying Abstractions of Timed Systems. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1996, pp:546-562 [Conf]
  5. Adnan Aziz, Serdar Tasiran, Robert K. Brayton
    BDD Variable Ordering for Interacting Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:283-288 [Conf]
  6. Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    HSIS: A BDD-Based Environment for Formal Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:454-459 [Conf]
  7. Serdar Tasiran, Yuan Yu, Brannon Batson
    Using a formal specification and a model checker to monitor and direct simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:356-361 [Conf]
  8. Soner Yaldiz, Alper Demir, Serdar Tasiran, Paolo Ienne, Yusuf Leblebici
    Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:135-140 [Conf]
  9. Tayfun Elmas, Shaz Qadeer, Serdar Tasiran
    Goldilocks: Efficiently Computing the Happens-Before Relation Using Locksets. [Citation Graph (0, 0)][DBLP]
    FATES/RV, 2006, pp:193-208 [Conf]
  10. Serdar Tasiran, Tayfun Elmas, Guven Bolukbasi, M. Erkan Keremoglu
    A Novel Test Coverage Metric for Concurrently-Accessed Software Components. [Citation Graph (0, 0)][DBLP]
    FATES, 2005, pp:62-71 [Conf]
  11. Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani, Serdar Tasiran
    An Assume-Guarantee Rule for Checking Simulation. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1998, pp:421-432 [Conf]
  12. Ellen Sentovich, David L. Dill, Serdar Tasiran
    Formal verification meets simulation (tutorial abstract). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:221- [Conf]
  13. Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer
    A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:82-88 [Conf]
  14. Shaz Qadeer, Serdar Tasiran
    Promising Directions in Hardware Design Verification (invited). [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:381-387 [Conf]
  15. Tayfun Elmas, Serdar Tasiran, Shaz Qadeer
    VYRD: verifYing concurrent programs by runtime refinement-violation detection. [Citation Graph (0, 0)][DBLP]
    PLDI, 2005, pp:27-37 [Conf]
  16. Serdar Tasiran, Kurt Keutzer
    Coverage Metrics for Functional Validation of Hardware Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:4, pp:36-45 [Journal]
  17. Serdar Tasiran, Yuan Yu, Brannon Batson
    Linking Simulation with Formal Verification at a Higher Level. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:472-482 [Journal]
  18. Tayfun Elmas, Serdar Tasiran
    VyrdMC: Driving Runtime Refinement Checking with Model Checkers. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:144, n:4, pp:41-56 [Journal]
  19. Serdar Tasiran, Shaz Qadeer
    Runtime Refinement Checking of Concurrent Data Structures. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2005, v:113, n:, pp:163-179 [Journal]
  20. Rajeev Joshi, Leslie Lamport, John Matthews, Serdar Tasiran, Mark R. Tuttle, Yuan Yu
    Checking Cache-Coherence Protocols with TLA+. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2003, v:22, n:2, pp:125-131 [Journal]
  21. Tamara Munzner, François Guimbretière, Serdar Tasiran, Li Zhang, Yunhong Zhou
    TreeJuxtaposer: scalable tree comparison using Focus+Context with guaranteed visibility. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Graph., 2003, v:22, n:3, pp:453-462 [Journal]
  22. Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani, Serdar Tasiran
    An assume-guarantee rule for checking simulation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2002, v:24, n:1, pp:51-64 [Journal]
  23. Tayfun Elmas, Shaz Qadeer, Serdar Tasiran
    Goldilocks: a race and transaction-aware java runtime. [Citation Graph (0, 0)][DBLP]
    PLDI, 2007, pp:245-255 [Conf]

  24. A classification of concurrency bugs in java benchmarks by developer intent. [Citation Graph (, )][DBLP]


  25. An annotation assistant for interactive debugging of programs with common synchronization idioms. [Citation Graph (, )][DBLP]


  26. A calculus of atomic actions. [Citation Graph (, )][DBLP]


  27. Simplifying Linearizability Proofs with Reduction and Abstraction. [Citation Graph (, )][DBLP]


  28. Rollback Atomicity. [Citation Graph (, )][DBLP]


  29. Tressa: Claiming the Future. [Citation Graph (, )][DBLP]


  30. Fast Monte Carlo Estimation of Timing Yield: Importance Sampling with Stochastic Logical Effort (ISLE) [Citation Graph (, )][DBLP]


Search in 0.157secs, Finished in 0.158secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002