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Vigyan Singhal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vigyan Singhal, Alan Jay Smith
    Analysis of Locking Behavior in Three Real Database Systems. [Citation Graph (1, 25)][DBLP]
    VLDB J., 1997, v:6, n:1, pp:40-52 [Journal]
  2. Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz
    Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists. [Citation Graph (0, 0)][DBLP]
    CAV, 1999, pp:72-83 [Conf]
  3. Jason Baumgartner, Anson Tripp, Adnan Aziz, Vigyan Singhal, Flemming Andersen
    An Abstraction Algorithm for the Verification of Generalized C-Slow Designs. [Citation Graph (0, 0)][DBLP]
    CAV, 2000, pp:5-19 [Conf]
  4. Adnan Aziz, Vigyan Singhal, Felice Balarin
    It Usually Works: The Temporal Logic of Stochastic Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 1995, pp:155-165 [Conf]
  5. Adnan Aziz, Thomas R. Shiple, Vigyan Singhal
    Formula-Dependent Equivalence for Compositional CTL Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 1994, pp:324-337 [Conf]
  6. Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton
    Verifying Continuous Time Markov Chains. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:269-276 [Conf]
  7. Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal
    BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. [Citation Graph (0, 0)][DBLP]
    CAV, 1998, pp:244-255 [Conf]
  8. Vigyan Singhal, Carl Pixley
    The Verifiacation Problem for Safe Replaceability. [Citation Graph (0, 0)][DBLP]
    CAV, 1994, pp:311-323 [Conf]
  9. Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    HSIS: A BDD-Based Environment for Formal Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:454-459 [Conf]
  10. Tai-Hung Liu, Khurram Sajid, Adnan Aziz, Vigyan Singhal
    Optimizing Designs Containing Black Boxes. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:113-116 [Conf]
  11. Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton
    The Validity of Retiming Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:316-321 [Conf]
  12. Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal
    BDS: a BDD-based logic optimization system. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:92-97 [Conf]
  13. Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton
    Using Combinational Verification for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:138-144 [Conf]
  14. Praveen Yalagandula, Adnan Aziz, Vigyan Singhal
    Automatic Lighthouse Generation for Directed State Space Search. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:237-242 [Conf]
  15. Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Equivalences for Fair Kripke Structures. [Citation Graph (0, 0)][DBLP]
    ICALP, 1994, pp:364-375 [Conf]
  16. Jerry R. Burch, Vigyan Singhal
    Robust latch mapping for combinational equivalence checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:563-569 [Conf]
  17. Jerry R. Burch, Vigyan Singhal
    Tight integration of combinational verification methods. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:570-576 [Conf]
  18. Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert K. Brayton, Adnan Aziz, Alberto L. Sangiovanni-Vincentelli
    Sequential optimisation without state space exploration. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:208-215 [Conf]
  19. Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton
    Multi-level synthesis for safe replaceability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:442-449 [Conf]
  20. Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton
    On the optimization power of retiming and resynthesis transformations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:402-407 [Conf]
  21. Vigyan Singhal, Sharad Malik, Robert K. Brayton
    The case for retiming with explicit reset circuitry. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:618-625 [Conf]
  22. Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton
    Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:255-261 [Conf]
  23. Shaz Qadeer, Robert K. Brayton, Vigyan Singhal
    Latch Redundancy Removal Without Global Reset. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:432-439 [Conf]
  24. Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton
    Heuristic Minimization of Synchronous Relations. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:428-433 [Conf]
  25. Gitanjali Swamy, Robert K. Brayton, Vigyan Singhal
    Incremental methods for FSM traversal. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:590-0 [Conf]
  26. Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal
    BDD Decomposition for Efficient Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:626-0 [Conf]
  27. Vigyan Singhal, Robert K. Brayton, Carl Pixley
    Power-Up Delay for Retiming Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:566-569 [Conf]
  28. Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Formula-Dependent Equivalence for Compositional CTL Model Checking. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2002, v:21, n:2, pp:193-224 [Journal]
  29. Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz
    An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2003, v:23, n:1, pp:39-65 [Journal]
  30. Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal
    BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2003, v:22, n:3, pp:205-224 [Journal]
  31. Carl Pixley, Vigyan Singhal
    Model Checking: A Hardware Design Perspective. [Citation Graph (0, 0)][DBLP]
    STTT, 1999, v:2, n:3, pp:288-306 [Journal]
  32. Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton
    Theory of safe replacements for sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:249-265 [Journal]
  33. Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton
    Model-checking continous-time Markov chains. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Log., 2000, v:1, n:1, pp:162-170 [Journal]
  34. Tai-Hung Liu, Adnan Aziz, Vigyan Singhal
    Optimizing designs containing black boxes. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:591-601 [Journal]
  35. Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton
    Sequential optimization in the absence of global reset. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:2, pp:222-251 [Journal]

  36. Exploiting power-up delay for sequential optimization. [Citation Graph (, )][DBLP]


  37. Formal Verification of a Public-Domain DDR2 Controller Design. [Citation Graph (, )][DBLP]


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