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Russell Tessier: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jian Liang, Sriram Swaminathan, Russell Tessier
    aSOC: A Scalable, Single-Chip Communications Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:37-46 [Conf]
  2. Ian G. Harris, Russell Tessier
    Interconnect testing in cluster-based FPGA architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:49-54 [Conf]
  3. Murali Kudlugi, Charles Selvidge, Russell Tessier
    Static Scheduling of Multiple Asynchronous Domains For Functional Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:647-652 [Conf]
  4. Jian Liang, Russell Tessier, Dennis Goeckel
    A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:91-100 [Conf]
  5. Jian Liang, Russell Tessier, Oskar Mencer
    Floating Point Unit Generation and Evaluation for FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:185-194 [Conf]
  6. Weifeng Xu, Ramshankar Ramanarayanan, Russell Tessier
    Adaptive Fault Recovery for Networked Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:143-0 [Conf]
  7. Lilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier
    An adaptive Reed-Solomon errors-and-erasures decoder. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:150-158 [Conf]
  8. Vijay Lakamraju, Russell Tessier
    Tolerating operational faults in cluster-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:187-194 [Conf]
  9. Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne Burleson
    A dynamically reconfigurable adaptive viterbi decoder. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:227-236 [Conf]
  10. Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy
    Power-aware RAM mapping for FPGA embedded memory blocks. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:189-198 [Conf]
  11. Kevin Oo Tinmaung, David Howland, Russell Tessier
    Power-aware FPGA logic synthesis using binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:148-155 [Conf]
  12. Srini Krishnamoorthy, Sriram Swaminathan, Russell Tessier
    Area-Optimized Technology Mapping for Hybrid FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:181-190 [Conf]
  13. Ramaswamy Ramaswamy, Russell Tessier
    The Integration of SystemC and Hardware-Assisted Verification. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1007-1016 [Conf]
  14. Russell Tessier, Heather Giza
    Balancing Logic Utilization and Area Efficiency in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:535-544 [Conf]
  15. Aiyappan Natarajan, David Jasinski, Wayne Burleson, Russell Tessier
    A hybrid adiabatic content addressable memory for ultra low-power applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:72-75 [Conf]
  16. Ian G. Harris, Russell Tessier
    Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:472-475 [Conf]
  17. Murali Kudlugi, Charles Selvidge, Russell Tessier
    Static Scheduling of Multi-Domain Memories For Functional Verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:2-9 [Conf]
  18. Andrew Laffely, Jian Liang, Russell Tessier, Wayne Burleson
    Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2003, pp:105-108 [Conf]
  19. Steve Ward, Karim Abdalla, Rajeev Dujari, Michael Fetterman, Frank Honoré, Ricardo Jenez, Philippe Laffont, Ken Mackenzie, Chris Metcalf, Milan Minsky, John Nguyen, John Pezaris, Gill A. Pratt, Russell Tessier
    The NuMesh: A Modular, Scalable Communications Substrate. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1993, pp:230-239 [Conf]
  20. Russell Tessier
    Frontier: A Fast Placement System for FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:125-136 [Conf]
  21. Atul Maheshwari, Wayne Burleson, Russell Tessier
    Trading off Reliability and Power-Consumption in Ultra-low Power Systems. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:361-366 [Conf]
  22. Ian G. Harris, Premachandran R. Menon, Russell Tessier
    BIST-based delay path testing in FPGA architectures. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:932-938 [Conf]
  23. Russell Tessier
    Incremental Compilation for Logic Emulation. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:236-241 [Conf]
  24. Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanono, David M. Hoki, Anant Agarwal
    Logic emulation with virtual wires. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:6, pp:609-626 [Journal]
  25. Ian G. Harris, Russell Tessier
    Testing and diagnosis of interconnect faults in cluster-based FPGA architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:11, pp:1337-1343 [Journal]
  26. Srini Krishnamoorthy, Russell Tessier
    Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:545-559 [Journal]
  27. Murali Kudlugi, Russell Tessier
    Static scheduling of multidomain circuits for fast functional verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:11, pp:1253-1268 [Journal]
  28. Premachandran R. Menon, Weifeng Xu, Russell Tessier
    Design-specific path delay testing in lookup-table-based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:867-877 [Journal]
  29. Russell Tessier
    Fast placement approaches for FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:2, pp:284-305 [Journal]
  30. Navin Vemuri, Priyank Kalla, Russell Tessier
    BDD-based logic synthesis for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:501-525 [Journal]
  31. Jian Liang, Andrew Laffely, S. Srinivasan, Russell Tessier
    An architecture and compiler for scalable on-chip communication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:711-726 [Journal]
  32. Atul Maheshwari, Wayne Burleson, Russell Tessier
    Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:299-311 [Journal]
  33. Russell Tessier, David Jasinski, Atul Maheshwari, Aiyappan Natarajan, Weifeng Xu, Wayne P. Burleson
    An energy-aware active smart card. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1190-1199 [Journal]
  34. Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne P. Burleson
    A reconfigurable, power-efficient adaptive Viterbi decoder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:484-488 [Journal]
  35. Weifeng Xu, Russell Tessier
    Tetris: a new register pressure control technique for VLIW processors. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:113-122 [Conf]
  36. Romain Vaslin, Guy Gogniat, Eduardo Wanderley Neto, Russell Tessier, Wayne P. Burleson
    Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:146-153 [Conf]

  37. A monitor interconnect and support subsystem for multicore processors. [Citation Graph (, )][DBLP]


  38. Multicore soft error rate stabilization using adaptive dual modular redundancy. [Citation Graph (, )][DBLP]


  39. High-efficiency protection solution for off-chip memory in embedded systems. [Citation Graph (, )][DBLP]


  40. Establishing Chain of Trust in Reconfigurable Hardware. [Citation Graph (, )][DBLP]


  41. Application Specific Customization and Scalability of Soft Multiprocessors. [Citation Graph (, )][DBLP]


  42. Scalable network virtualization using FPGAs. [Citation Graph (, )][DBLP]


  43. CMOS vs Nano: comrades or rivals? [Citation Graph (, )][DBLP]


  44. Thermal-aware voltage droop compensation for multi-core architectures. [Citation Graph (, )][DBLP]


  45. An Interactive Approach to Timing Accurate PCI-X Simulation. [Citation Graph (, )][DBLP]


  46. Design of a Secure Router System for Next-Generation Networks. [Citation Graph (, )][DBLP]


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