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Michel Langevin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. K. D. Anon, N. Boulerice, Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Ying Xu, Zijian Zhou
    MDG Tools for the Verification of RTL Designs. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:433-436 [Conf]
  2. Michel Langevin
    Automated RTL Verification Based on Predicate Calculus. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:116-125 [Conf]
  3. Michel Langevin, Eduard Cerny
    Comparing Generic State Machines. [Citation Graph (0, 0)][DBLP]
    CAV, 1991, pp:466-476 [Conf]
  4. Francisco Corella, Michel Langevin, Eduard Cerny, Zijian Zhou, Xiaoyu Song
    State enumeration with abstract descriptions of state machines. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:146-160 [Conf]
  5. Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Gabriela Nicolescu
    Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:48-53 [Conf]
  6. Michel Langevin, Eduard Cerny, Jörg Wilberg, Heinrich Theodor Vierhaus
    Local microcode generation in system design. [Citation Graph (0, 0)][DBLP]
    Code Generation for Embedded Processors, 1994, pp:171-187 [Conf]
  7. Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane, Michel Langevin, Damien Lyonnard
    Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:58-63 [Conf]
  8. Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Olivier Benny, Damien Lyonnard, Bruno Lavigueur, David Lo
    Distributed object models for multi-processor SoC's, with application to low-power multimedia wireless systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:482-487 [Conf]
  9. Michel Langevin, Eduard Cerny
    An Extended OBDD Representation for Extended FSMs. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:208-213 [Conf]
  10. Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Zijian Zhou
    Verification with Abstract State Machines Using MDGs. [Citation Graph (0, 0)][DBLP]
    Formal Hardware Verification, 1997, pp:79-113 [Conf]
  11. Zijian Zhou, Xiaoyu Song, Sofiène Tahar, Eduard Cerny, Francisco Corella, Michel Langevin
    Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:233-247 [Conf]
  12. Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny, Michel Langevin
    Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:106-111 [Conf]
  13. Zijian Zhou, Xiaoyu Song, Francisco Corella, Eduard Cerny, Michel Langevin
    Partitioning transition relations efficiently and automatically. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:106-111 [Conf]
  14. Michel Langevin, Eduard Cerny
    A Recursive Technique for Computing Lower-Bound Performance of Schedules. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:16-20 [Conf]
  15. Michel Langevin, Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny
    Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:20-26 [Conf]
  16. Paul-Gerhard Plöger, Jörg Wilberg, Michel Langevin, Raul Camposano
    WWW based structuring of codesigns. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:138-143 [Conf]
  17. Francisco Corella, Zijian Zhou, Xiaoyu Song, Michel Langevin, Eduard Cerny
    Multiway Decision Graphs for Automated Hardware Verification. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:10, n:1, pp:7-46 [Journal]
  18. Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou, Michel Langevin, Otmane Aït Mohamed
    Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:956-972 [Journal]
  19. Michel Langevin, Eduard Cerny
    A recursive technique for computing lower-bound performance of schedules. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:4, pp:443-455 [Journal]
  20. Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Damien Lyonnard, Olivier Benny, Bruno Lavigueur, David Lo, Giovanni Beltrame, V. Gagne, Gabriela Nicolescu
    Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:667-680 [Journal]

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