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Alexander Saldanha: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Adnan Aziz, Felice Balarin, Robert K. Brayton, M. D. DiBenedetto, Alexander Saldanha
    Supervisory Control of Finite State Machines. [Citation Graph (0, 0)][DBLP]
    CAV, 1995, pp:279-292 [Conf]
  2. Kurt Keutzer, Sharad Malik, Alexander Saldanha
    Is Redundancy Necessary to Reduce Delay. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:228-234 [Conf]
  3. William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Delay Fault Coverage and Performance Tradeoffs. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:446-452 [Conf]
  4. Luciano Lavagno, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli
    Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:254-260 [Conf]
  5. Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:173-176 [Conf]
  6. Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:245-248 [Conf]
  7. Alexander Saldanha, Heather Harkness, Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Performance Optimization Using Exact Sensitization. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:425-429 [Conf]
  8. Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    A Framework for Satisfying Input and Output Encoding Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:170-175 [Conf]
  9. Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Multi-level Logic Simplification Using Don't Cares and Filters. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:277-282 [Conf]
  10. Alberto L. Sangiovanni-Vincentelli, Patrick C. McGeer, Alexander Saldanha
    Verification of Electronic Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:106-111 [Conf]
  11. Wilsin Gosti, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa, Alexander Saldanha
    An Exact Input Encoding Algorithm for BDDs Representing FSMs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:294-300 [Conf]
  12. Alok Agrawal, Alexander Saldanha, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    Compact and complete test set generation for multiple stuck-faults. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:212-219 [Conf]
  13. Luca P. Carloni, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli
    Trace driven logic synthesis&mdashapplication to power minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:581-588 [Conf]
  14. Luca P. Carloni, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli
    A methodology for correct-by-construction latency insensitive design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:309-315 [Conf]
  15. Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton
    Approximate timing analysis of combinational circuits under the XBD0 model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:176-181 [Conf]
  16. Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin
    Partial scan delay fault testing of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:728-735 [Conf]
  17. Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia
    Fast discrete function evaluation using decision diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:402-407 [Conf]
  18. Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:180-183 [Conf]
  19. Alexander Saldanha
    Functional timing optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:539-543 [Conf]
  20. Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng
    Timing Optimization with Testability Considerations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:460-463 [Conf]
  21. Eugene Goldberg, Alexander Saldanha
    Timing Analysis with Implicitly Specified False Paths. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:518-522 [Conf]
  22. Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Functional clock schedule optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:93-98 [Conf]
  23. Kurt Keutzer, Sharad Malik, Alexander Saldanha
    Is redundancy necessary to reduce delay? [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:427-435 [Journal]
  24. Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin
    Partial-scan delay fault testing of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1184-1199 [Journal]
  25. William K. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Delay fault coverage, test set size, and performance trade-offs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:32-44 [Journal]
  26. Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Circuit structure relations to redundancy and delay. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:875-883 [Journal]
  27. Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Satisfaction of input and output encoding constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:589-602 [Journal]
  28. Tiziano Villa, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Symbolic two-level minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:692-708 [Journal]

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