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Gary D. Hachtel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
    VIS: A System for Verification and Synthesis. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:428-432 [Conf]
  2. Abelardo Pardo, Gary D. Hachtel
    Automatic Abstraction Techniques for Propositional µ-calculus Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 1997, pp:12-23 [Conf]
  3. Chao Wang, Roderick Bloem, Gary D. Hachtel, Kavita Ravi, Fabio Somenzi
    Divide and Compose: SCC Refinement for Language Emptiness. [Citation Graph (0, 0)][DBLP]
    CONCUR, 2001, pp:456-471 [Conf]
  4. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi
    Algorithms for Approximate FSM Traversal. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:25-30 [Conf]
  5. David Gregory, Karen A. Bartlett, Aart J. de Geus, Gary D. Hachtel
    SOCRATES: a system for automatically synthesizing and optimizing combinational logic. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:79-85 [Conf]
  6. Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
    Probabilistic Analysis of Large Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:270-275 [Conf]
  7. Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino
    Computing the Maximum Power Cycles of a Sequential Circuit. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:23-28 [Conf]
  8. Abelardo Pardo, Gary D. Hachtel
    Incremental CTL Model Checking Using BDD Subsetting. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:457-462 [Conf]
  9. Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel
    Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:620-623 [Conf]
  10. Chao Wang, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi
    Refining the SAT decision ordering for bounded model checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:535-538 [Conf]
  11. Jae-Young Jang, In-Ho Moon, Gary D. Hachtel
    Iterative Abstraction-Based CTL Model Checking. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:502-0 [Conf]
  12. R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
    Timing Analysis of Combinational Circuits using ADD's. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:625-629 [Conf]
  13. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi
    A State Space Decomposition Algorithm for Approximate FSM Traversal. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:137-141 [Conf]
  14. Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
    Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:214-218 [Conf]
  15. Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
    VIS. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:248-256 [Conf]
  16. In-Ho Moon, Gary D. Hachtel, Fabio Somenzi
    Border-Block Triangular Form and Conjunction Schedule in Image Computation. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:73-90 [Conf]
  17. Kavita Ravi, Abelardo Pardo, Gary D. Hachtel, Fabio Somenzi
    Modular Verification of Multipliers. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:49-63 [Conf]
  18. Chao Wang, Gary D. Hachtel
    Sharp Disjunctive Decomposition for Language Emptiness Checking. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2002, pp:106-122 [Conf]
  19. R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
    Algebraic decision diagrams and their applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:188-191 [Conf]
  20. R. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
    A symbolic method to reduce power consumption of circuits containing false paths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:368-371 [Conf]
  21. Hyunwoo Cho, Gary D. Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric M. Schwarz, Fabio Somenzi
    ATPG Aspects of FSM Verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:134-137 [Conf]
  22. Gary D. Hachtel, Mariano Hermida de la Rica, Abelardo Pardo, Massimo Poncino, Fabio Somenzi
    Re-encoding sequential circuits to reduce power dissipation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:70-73 [Conf]
  23. Gary D. Hachtel, Fabio Somenzi
    A symbolic algorithm for maximum flow in 0-1 networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:403-406 [Conf]
  24. Seh-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi
    Extended BDD's: Trading off Canonicity for Structure in Verification Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:464-467 [Conf]
  25. Seon-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi
    Variable Ordering and Selection for FSM Traversal. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:476-479 [Conf]
  26. Woohyuk Lee, Abelardo Pardo, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi
    Tearing based automatic abstraction for CTL model checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:76-81 [Conf]
  27. In-Ho Moon, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi, Jun Yuan, Carl Pixley
    Approximate reachability don't cares for CTL model checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:351-358 [Conf]
  28. June-Kyung Rho, Gary D. Hachtel, Fabio Somenzi
    Don't Care Sequences and the Optimization of Interacting Finite State Machines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:418-421 [Conf]
  29. Chao Wang, Gary D. Hachtel, Fabio Somenzi
    The Compositional Far Side of Image Computation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:334-341 [Conf]
  30. Chao Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi
    Improving Ariadneýs Bundle by Following Multiple Threads in Abstraction Refinement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:408-415 [Conf]
  31. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi
    A Structural Approach to State Space Decomposition for Approximate Reachability Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:236-239 [Conf]
  32. Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi
    Redundancy Identification and Removal Based on Implicit State Enumeration. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:77-80 [Conf]
  33. Chao Wang, Gary D. Hachtel, Fabio Somenzi
    Fine-Grain Abstraction and Sequential Don't Cares for Large Scale Model Checking. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:112-118 [Conf]
  34. Michael R. Lightner, Gary D. Hachtel, Richard H. Byrd, Michel Heydemann
    A Theory and Algorithmic Frame for Switch Level Simulation. [Citation Graph (0, 0)][DBLP]
    IMACS European Simulation Meeting, 1984, pp:151-159 [Conf]
  35. R. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi
    Symbolic computation of logic implications for technology-dependent low-power synthesis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:163-168 [Conf]
  36. Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi
    CMOS dynamic power estimation based on collapsible current source transistor modeling. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:111-116 [Conf]
  37. Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi
    Fast Sequential ATPG Based on Implicit State Enumeration. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:67-74 [Conf]
  38. R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
    Algebraic Decision Diagrams and Their Applications. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:10, n:2/3, pp:171-206 [Journal]
  39. Gary D. Hachtel, Fabio Somenzi
    A Symbolic Algorithms for Maximum Flow in 0-1 Networks. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:10, n:2/3, pp:207-219 [Journal]
  40. Bernard Plessier, Gary D. Hachtel, Fabio Somenzi
    Extended BDDs: Trading off Canonicity for Structure in Verification Algorithms. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1994, v:4, n:2, pp:167-185 [Journal]
  41. Chao Wang, Roderick Bloem, Gary D. Hachtel, Kavita Ravi, Fabio Somenzi
    Compositional SCC Analysis for Language Emptiness. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2006, v:28, n:1, pp:5-36 [Journal]
  42. R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
    Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1101-1115 [Journal]
  43. Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang
    Multi-level logic minimization using implicit don't cares. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:723-740 [Journal]
  44. Karen A. Bartlett, William W. Cohen, Aart J. de Geus, Gary D. Hachtel
    Synthesis and Optimization of Multilevel Logic under Timing Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:582-596 [Journal]
  45. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi
    Automatic state space decomposition for approximate FSM traversal based on circuit analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1451-1464 [Journal]
  46. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi
    Algorithms for approximate FSM traversal based on state space decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1465-1478 [Journal]
  47. Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi
    Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:935-945 [Journal]
  48. Xuejun Du, Gary D. Hachtel, Bill Lin, A. Richard Newton
    MUSE: a multilevel symbolic encoding algorithm for state assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:28-38 [Journal]
  49. Gary D. Hachtel, Reily M. Jacoby
    Verification algorithms for VLSI synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:5, pp:616-640 [Journal]
  50. Gary D. Hachtel, Reily M. Jacoby, Kurt Keutzer, Christopher R. Morrison
    On properties of algebraic transformations and the synthesis of multifault-irredundant circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:3, pp:313-321 [Journal]
  51. Gary D. Hachtel, Christopher R. Morrison
    Linear complexity algorithms for hierarchical routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:64-80 [Journal]
  52. Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
    Markovian analysis of large finite state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1479-1493 [Journal]
  53. Gary D. Hachtel, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
    An Algorithm for Optimal PLA Folding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1982, v:1, n:2, pp:63-77 [Journal]
  54. Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel
    Exact calculation of synchronizing sequences based on binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1024-1034 [Journal]
  55. June-Kyung Rho, Gary D. Hachtel, Fabio Somenzi, Reily M. Jacoby
    Exact and heuristic algorithms for the minimization of incompletely specified state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:167-177 [Journal]
  56. Chai Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi
    Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2297-2316 [Journal]

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