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Yuji Kukimoto: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
    VIS: A System for Verification and Synthesis. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:428-432 [Conf]
  2. Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka
    A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:76-85 [Conf]
  3. Yuji Kukimoto, Robert K. Brayton
    Exact Required Time Analysis via False Path Detection. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:220-225 [Conf]
  4. Yuji Kukimoto, Robert K. Brayton
    Hierarchical Functional Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:580-585 [Conf]
  5. Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar
    Delay-Optimal Technology Mapping by DAG Covering. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:348-351 [Conf]
  6. Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton
    Combinational Verification based on High-Level Functional Specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:803-0 [Conf]
  7. Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
    VIS. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:248-256 [Conf]
  8. Masahiro Fujita, Yuji Kukimoto
    Patching Method for Lookup-Table Type FPLs. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:61-70 [Conf]
  9. Pinhong Chen, Yuji Kukimoto, Kurt Keutzer
    Refining switching window by time slots for crosstalk noise calculation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:583-586 [Conf]
  10. Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen
    Application of Boolean Unification to Combinational Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:510-513 [Conf]
  11. Yuji Kukimoto, Robert K. Brayton
    Timing-safe false path removal for combinational modules. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:544-550 [Conf]
  12. Yuji Kukimoto, Masahiro Fujita
    Rectification method for lookup-table type FPGA's. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:54-61 [Conf]
  13. Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton
    A redesign technique for combinational circuits based on gate reconnections. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:632-637 [Conf]
  14. Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton
    Approximate timing analysis of combinational circuits under the XBD0 model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:176-181 [Conf]
  15. Pinhong Chen, Yuji Kukimoto, Chin-Chi Teng, Kurt Keutzer
    On convergence of switching windows computation in presence of crosstalk noise. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:84-89 [Conf]

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