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Gitanjali Swamy: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
    VIS: A System for Verification and Synthesis. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:428-432 [Conf]
  2. Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
    VIS. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:248-256 [Conf]
  3. Gitanjali Swamy, Robert K. Brayton
    Incremental formal design verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:458-465 [Conf]
  4. Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton
    Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:255-261 [Conf]
  5. Gitanjali Swamy, Robert K. Brayton, Vigyan Singhal
    Incremental methods for FSM traversal. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:590-0 [Conf]
  6. Gitanjali Swamy
    Formal Verification of Digital Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:213-217 [Conf]
  7. Gitanjali Swamy, Stephen A. Edwards, Robert K. Brayton
    Efficient Verification and Synthesis using Design Commonalities. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:542-551 [Conf]

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