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Publications of Author

1. Sérgio Vale Aguiar Campos, Edmund M. Clarke, Marius Minea
   The Verus Tool: A Quantitative Approach to the Formal Verification of Real-Time Systems. [Citation Graph (0, 0)][DBLP]
   CAV, 1997, pp:452-455 [Conf]
   
2. Marius Minea
   Partial Order Reduction for Model Checking of Timed Automata. [Citation Graph (0, 0)][DBLP]
   CONCUR, 1999, pp:431-446 [Conf]
   
3. Blaise Genest, Marius Minea, Anca Muscholl, Doron Peled
   Specifying and Verifying Partial Order Properties Using Template MSCs. [Citation Graph (0, 0)][DBLP]
   FoSSaCS, 2004, pp:195-210 [Conf]
   
4. Thomas A. Henzinger, Marius Minea, Vinayak S. Prabhu
   Assume-Guarantee Reasoning for Hierarchical Hybrid Systems. [Citation Graph (0, 0)][DBLP]
   HSCC, 2001, pp:275-290 [Conf]
   
5. Robert P. Kurshan, Vladimir Levin, Marius Minea, Doron Peled, Hüsnü Yenigün
   Verifying hardware in its software context. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1997, pp:742-749 [Conf]
   
6. Sérgio Vale Aguiar Campos, Edmund M. Clarke, Wilfredo R. Marrero, Marius Minea
   Verifying the performance of the PCI local bus using symbolic techniques. [Citation Graph (0, 0)][DBLP]
   ICCD, 1995, pp:72-78 [Conf]
   
7. Somesh Jha, Yuan Lu, Marius Minea, Edmund M. Clarke
   Equivalence Checking Using Abstract BDDs. [Citation Graph (0, 0)][DBLP]
   ICCD, 1997, pp:332-337 [Conf]
   
8. Sérgio Vale Aguiar Campos, Edmund M. Clarke, Wilfredo R. Marrero, Marius Minea
   Verus: A Tool for Quantitative Analysis of Finite-State Real-Time Systems. [Citation Graph (0, 0)][DBLP]
   Workshop on Languages, Compilers, & Tools for Real-Time Systems, 1995, pp:70-78 [Conf]
   
9. Danièle Beauquier, Marie Duflot, Marius Minea
   A Probabilistic Property-Specific Approach to Information Flow. [Citation Graph (0, 0)][DBLP]
   MMM-ACNS, 2005, pp:206-220 [Conf]
   
10. Sérgio Vale Aguiar Campos, Edmund M. Clarke, Wilfredo R. Marrero, Marius Minea, Hiromi Hiraishi
    Computing Quantitative Characteristics of Finite-State Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1994, pp:266-270 [Conf]
    
11. Jonas Elmqvist, Simin Nadjm-Tehrani, Marius Minea
    Safety Interfaces for Component-Based Systems. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 2005, pp:246-260 [Conf]
    
12. Robert P. Kurshan, Vladimir Levin, Marius Minea, Doron Peled, Hüsnü Yenigün
    Static Partial Order Reduction. [Citation Graph (0, 0)][DBLP]
    TACAS, 1998, pp:345-357 [Conf]
    
13. Sérgio Vale Aguiar Campos, Marcio Teixeira, Marius Minea, Andreas Kuehlmann, Edmund M. Clarke
    Model Checking Semi-Continuous Time Models Using BDDs. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 1999, v:23, n:2, pp:- [Journal]
    
14. Robert P. Kurshan, Vladimir Levin, Marius Minea, Doron Peled, Hüsnü Yenigün
    Combining Software and Hardware Verification Techniques. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2002, v:21, n:3, pp:251-280 [Journal]
    
15. Sérgio Vale Aguiar Campos, Edmund M. Clarke, Marius Minea
    Symbolic Techniques for Formally Verifying Industrial Systems. [Citation Graph (0, 0)][DBLP]
    Sci. Comput. Program., 1997, v:29, n:1-2, pp:79-98 [Journal]
    
16. Edmund M. Clarke, Orna Grumberg, Marius Minea, Doron Peled
    State Space Reduction Using Partial Order Techniques. [Citation Graph (0, 0)][DBLP]
    STTT, 1999, v:2, n:3, pp:279-287 [Journal]
    
17. Catalin Dima, Marius Minea, Ferucio Laurentiu Tiplea
    Preface. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2007, v:186, n:, pp:1-2 [Journal]
    
18. 
    Synthesis of VHDL concurrent processes. [Citation Graph (, )][DBLP]
    
    
19. 
    A Formal Approach for Automated Reasoning about Off-Line and Undetectable On-Line Guessing. [Citation Graph (, )][DBLP]
    
    
20. 
    A Calculus to Detect Guessing Attacks. [Citation Graph (, )][DBLP]
    
    
21. 
    Relooper: refactoring for loop parallelism in Java. [Citation Graph (, )][DBLP]