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Paolo Camurati:
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Publications of Author
- Paolo Camurati, M. Gilli, Paolo Prinetto, Matteo Sonza Reorda
The Use of Model Checking in ATPG for Sequential Circuits. [Citation Graph (0, 0)][DBLP] CAV, 1990, pp:86-95 [Conf]
- Gianpiero Cabodi, Paolo Camurati
Advancements in Symbolic Traversal Technique. [Citation Graph (0, 0)][DBLP] CHARME, 1993, pp:155-166 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Antonio Lioy, Massimo Poncino, Stefano Quer
A parallel approach to symbolic traversal based on set partitioning. [Citation Graph (0, 0)][DBLP] CHARME, 1997, pp:167-184 [Conf]
- Gianpiero Cabodi, Stefano Quer, Paolo Camurati
Transforming boolean relations by symbolic encoding. [Citation Graph (0, 0)][DBLP] CHARME, 1995, pp:161-170 [Conf]
- Paolo Camurati, Fulvio Corno, Paolo Prinetto
A Methodology for System-Level Design for Verifiability. [Citation Graph (0, 0)][DBLP] CHARME, 1993, pp:80-91 [Conf]
- Paolo Camurati, Fulvio Corno, Paolo Prinetto
Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation. [Citation Graph (0, 0)][DBLP] CHDL, 1993, pp:31-44 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Silvano Gai, Paolo Prinetto, Matteo Sonza Reorda
A New Model for Improving symbolic Product Machine Traversal. [Citation Graph (0, 0)][DBLP] DAC, 1992, pp:614-619 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer
Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits. [Citation Graph (0, 0)][DBLP] DAC, 1997, pp:728-733 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Can BDDs compete with SAT solvers on bounded model checking? [Citation Graph (0, 0)][DBLP] DAC, 2002, pp:117-122 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Auxiliary Variables for Extending Symbolic Traversal Techniques to Data Paths. [Citation Graph (0, 0)][DBLP] DAC, 1994, pp:289-293 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Improving Symbolic Traversals by Means of Activity Profiles. [Citation Graph (0, 0)][DBLP] DAC, 1999, pp:306-311 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Claudio Passerone, Stefano Quer
Computing Timed Transition Relations for Sequential Cycle-Based Simulation. [Citation Graph (0, 0)][DBLP] DATE, 1999, pp:8-12 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Biasing symbolic search by means of dynamic activity profiles. [Citation Graph (0, 0)][DBLP] DATE, 2001, pp:9-15 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Dynamic Scheduling and Clustering in Symbolic Image Computation. [Citation Graph (0, 0)][DBLP] DATE, 2002, pp:150-157 [Conf]
- Paolo Camurati, Fulvio Corno, Paolo Prinetto, C. Bayol, B. Soulas
System-Level Modeling and Verification: a Comprehensive Design Methodology. [Citation Graph (0, 0)][DBLP] EDAC-ETC-EUROASIC, 1994, pp:636-640 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto
Experiences in Prolog-Based DFT Rule Checking. [Citation Graph (0, 0)][DBLP] FJCC, 1986, pp:909-914 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Improved reachability analysis of large finite state machines. [Citation Graph (0, 0)][DBLP] ICCAD, 1996, pp:354-360 [Conf]
- Gianpiero Cabodi, Paolo Camurati
Exploiting Cofactoring for Efficient FSM Symbolic Traversal Based on the Transition Relation. [Citation Graph (0, 0)][DBLP] ICCD, 1993, pp:299-303 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Efficient State Space Pruning in Symbolic Backward Traversal. [Citation Graph (0, 0)][DBLP] ICCD, 1994, pp:230-235 [Conf]
- Gianpiero Cabodi, Luciano Lavagno, Enrico Macii, Massimo Poncino, Stefano Quer, Paolo Camurati, Ellen Sentovich
Enhancing FSM Traversal by Temporary Re-Encoding. [Citation Graph (0, 0)][DBLP] ICCD, 1996, pp:6-11 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Detecting hard faults with combined approximate forward/backward symbolic techniques. [Citation Graph (0, 0)][DBLP] ISCAS, 1994, pp:299-302 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
Sequential Circuit Diagnosis Based on Formal Verification Techniques. [Citation Graph (0, 0)][DBLP] ITC, 1992, pp:187-196 [Conf]
- Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Full-Symbolic ATPG for Large Circuits. [Citation Graph (0, 0)][DBLP] ITC, 1994, pp:980-988 [Conf]
- Paolo Camurati, Paolo Prinetto
Formal Verification of Hardware Correctness: Introduction and Survey of Current Research. [Citation Graph (0, 0)][DBLP] IEEE Computer, 1988, v:21, n:7, pp:8-19 [Journal]
- Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina
Industrial BIST of Embedded RAMs. [Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 1995, v:12, n:3, pp:86-95 [Journal]
- Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
The General Product Machine: a New Model for Symbolic FSM Traversal. [Citation Graph (0, 0)][DBLP] Formal Methods in System Design, 1998, v:12, n:3, pp:267-289 [Journal]
- Stefano Quer, Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Ellen Sentovich, Robert K. Brayton
Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks. [Citation Graph (0, 0)][DBLP] Formal Methods in System Design, 2000, v:17, n:2, pp:107-134 [Journal]
- Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda
TPDL: Extended Temporal Profile Description Language. [Citation Graph (0, 0)][DBLP] Softw., Pract. Exper., 1991, v:21, n:4, pp:355-374 [Journal]
- Gianpiero Cabodi, Stefano Quer, Paolo Camurati
Memory Optimization in Function and Set Manipulation with BDDs. [Citation Graph (0, 0)][DBLP] Softw., Pract. Exper., 1998, v:28, n:1, pp:99-120 [Journal]
- Gianpiero Cabodi, Paolo Camurati
Symbolic FSM traversals based on the transition relation. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:448-457 [Journal]
- Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Improving symbolic reachability analysis by means of activityprofiles. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1065-1075 [Journal]
- Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Improving the efficiency of BDD-based operators by means of partitioning. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:545-556 [Journal]
- Paolo Camurati, P. Gianoglio, R. Gianoglio, Paolo Prinetto
ESTA: an expert system for DFT rule verification. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:11, pp:1172-1180 [Journal]
- Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Auxiliary variables for BDD-based representation and manipulation of Boolean functions. [Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:309-340 [Journal]
Verification and synthesis of counters based on symbolic techniques. [Citation Graph (, )][DBLP]
Speeding up model checking by exploiting explicit and hidden verification constraints. [Citation Graph (, )][DBLP]
Computing subsets of equivalence classes for large FSMs. [Citation Graph (, )][DBLP]
Symbolic exploration of large circuits with enhanced forward/backward traversals. [Citation Graph (, )][DBLP]
Diagnosis oriented test pattern generation. [Citation Graph (, )][DBLP]
Trading-Off SAT Search and Variable Quantifications for Effective Unbounded Model Checking. [Citation Graph (, )][DBLP]
Automated abstraction by incremental refinement in interpolant-based model checking. [Citation Graph (, )][DBLP]
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