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Luca P. Carloni: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Luca P. Carloni, Kenneth L. McMillan, Alberto L. Sangiovanni-Vincentelli
    Latency Insensitive Protocols. [Citation Graph (0, 0)][DBLP]
    CAV, 1999, pp:123-133 [Conf]
  2. Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    On-chip communication design: roadblocks and avenues. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:75-76 [Conf]
  3. Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Performance analysis and optimization of latency insensitive systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:361-367 [Conf]
  4. Alessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Constraint-driven communication synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:783-788 [Conf]
  5. Alberto L. Sangiovanni-Vincentelli, Luca P. Carloni, Fernando De Bernardinis, Marco Sgroi
    Benefits and challenges for platform-based design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:409-414 [Conf]
  6. Alvise Bonivento, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Platform-based design of wireless sensor networks for industrial applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1103-1107 [Conf]
  7. Claudio Pinello, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1164-1169 [Conf]
  8. Albert Benveniste, Benoît Caillaud, Luca P. Carloni, Paul Caspi, Alberto L. Sangiovanni-Vincentelli
    Heterogeneous reactive systems modeling: capturing causality and the correctness of loosely time-triggered architectures (LTTA). [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2004, pp:220-229 [Conf]
  9. Albert Benveniste, Luca P. Carloni, Paul Caspi, Alberto L. Sangiovanni-Vincentelli
    Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2003, pp:35-50 [Conf]
  10. Albert Benveniste, Benoît Caillaud, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Tag machines. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2005, pp:255-263 [Conf]
  11. Alvise Bonivento, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Rialto: a bridge between description and implementation of control algorithms for wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2005, pp:183-186 [Conf]
  12. Albert Benveniste, Benoît Caillaud, Luca P. Carloni, Paul Caspi, Alberto L. Sangiovanni-Vincentelli, Stavros Tripakis
    Communication by sampling in time-sensitive distributed systems. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2006, pp:152-160 [Conf]
  13. Albert Benveniste, Benoît Caillaud, Luca P. Carloni, Paul Caspi, Alberto L. Sangiovanni-Vincentelli
    Causality and Scheduling Constraints in Heterogeneous Reactive Systems Modeling. [Citation Graph (0, 0)][DBLP]
    FMCO, 2003, pp:1-16 [Conf]
  14. Alessandro Pinto, Luca P. Carloni, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli
    Interchange Format for Hybrid Systems: Abstract Semantics. [Citation Graph (0, 0)][DBLP]
    HSCC, 2006, pp:491-506 [Conf]
  15. Alessandro Pinto, Alberto L. Sangiovanni-Vincentelli, Luca P. Carloni, Roberto Passerone
    Interchange Formats for Hybrid Systems: Review and Proposal. [Citation Graph (0, 0)][DBLP]
    HSCC, 2005, pp:526-541 [Conf]
  16. Luca P. Carloni, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli
    Trace driven logic synthesis&mdashapplication to power minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:581-588 [Conf]
  17. Luca P. Carloni, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli
    A methodology for correct-by-construction latency insensitive design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:309-315 [Conf]
  18. Evguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Negative thinking by incremental problem solving: application to unate covering. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:91-98 [Conf]
  19. Alessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Efficient Synthesis of Networks On Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:146-150 [Conf]
  20. Luca P. Carloni, Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:346-361 [Conf]
  21. Stefano Zanella, Andrea Neviani, Enrico Zanoni, Paolo Miliozzi, Edoardo Charbon, Carlo Guardiani, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Modeling of Substrate Noise Injected by Digital Libraries. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:488-0 [Conf]
  22. Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:47-52 [Conf]
  23. Luca P. Carloni
    The Role of Back-Pressure in Implementing Latency-Insensitive Systems. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:146, n:2, pp:61-80 [Journal]
  24. Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    A Framework for Modeling the Distributed Deployment of Synchronous Designs. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2006, v:28, n:2, pp:93-110 [Journal]
  25. Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Coping with Latency in SOC Design. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2002, v:22, n:5, pp:24-35 [Journal]
  26. Alvise Bonivento, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Platform based design for wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    MONET, 2006, v:11, n:4, pp:469-485 [Journal]
  27. Arlindo L. Oliveira, Luca P. Carloni, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli
    Exact Minimization of Binary Decision Diagrams Using Implicit Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:11, pp:1282-1296 [Journal]
  28. Luca P. Carloni, Kenneth L. McMillan, Alberto L. Sangiovanni-Vincentelli
    Theory of latency-insensitive design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1059-1076 [Journal]
  29. Edoardo Charbon, Paolo Miliozzi, Luca P. Carloni, Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli
    Modeling digital substrate noise injection in mixed-signal IC's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:301-310 [Journal]
  30. Evguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Negative thinking in branch-and-bound: the case of unate covering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:3, pp:281-294 [Journal]
  31. Rebecca L. Collins, Luca P. Carloni
    Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:410-415 [Conf]
  32. Assaf Shacham, Keren Bergman, Luca P. Carloni
    The Case for Low-Power Photonic Networks on Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:132-135 [Conf]
  33. Cheng-Hong Li, Rebecca L. Collins, Sampada Sonalkar, Luca P. Carloni
    Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:13-22 [Conf]
  34. Assaf Shacham, Keren Bergman, Luca P. Carloni
    On the Design of a Photonic Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:53-64 [Conf]

  35. Interconnect modeling for improved system-level design optimization. [Citation Graph (, )][DBLP]


  36. A heterogeneous parallel system running open mpi on a broadband network of embedded set-top devices. [Citation Graph (, )][DBLP]


  37. Distributed flit-buffer flow control for networks-on-chip. [Citation Graph (, )][DBLP]


  38. Virtual channels vs. multiple physical networks: a comparative analysis. [Citation Graph (, )][DBLP]


  39. A case study in distributed deployment of embedded software for camera networks. [Citation Graph (, )][DBLP]


  40. Exploiting local logic structures to optimize multi-core SoC floorplanning. [Citation Graph (, )][DBLP]


  41. Recursion-driven parallel code generation for multi-core platforms. [Citation Graph (, )][DBLP]


  42. PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks. [Citation Graph (, )][DBLP]


  43. A communication synthesis infrastructure for heterogeneous networked control systems and its application to building automation and control. [Citation Graph (, )][DBLP]


  44. Flexible filters: load balancing through backpressure for stream programs. [Citation Graph (, )][DBLP]


  45. Design Exploration of Optical Interconnection Networks for Chip Multiprocessors. [Citation Graph (, )][DBLP]


  46. Using functional independence conditions to optimize the performance of latency-insensitive systems. [Citation Graph (, )][DBLP]


  47. Photonic networks-on-chip: Opportunities and challenges. [Citation Graph (, )][DBLP]


  48. Networks-on-chip in emerging interconnect paradigms: Advantages and challenges. [Citation Graph (, )][DBLP]


  49. Analysis of photonic networks for a chip multiprocessor using scientific applications. [Citation Graph (, )][DBLP]


  50. CTC: An end-to-end flow control protocol for multi-core systems-on-chip. [Citation Graph (, )][DBLP]


  51. COSI: A Framework for the Design of Interconnection Networks. [Citation Graph (, )][DBLP]


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