The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Srilatha Manne: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Srilatha Manne, Artur Klauser, Dirk Grunwald
    Branch Prediction Using Selective Branch Inversion. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:48-56 [Conf]
  2. Olivier Coudert, Ramsey W. Haddad, Srilatha Manne
    New Algorithms for Gate Sizing: A Comparative Study. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:734-739 [Conf]
  3. Srilatha Manne, Dirk Grunwald, Fabio Somenzi
    Remembrance of Things Past: Locality and Memory in BDDs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:196-201 [Conf]
  4. Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino
    Computing the Maximum Power Cycles of a Sequential Circuit. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:23-28 [Conf]
  5. Eric Borch, Eric Tune, Srilatha Manne, Joel S. Emer
    Loose Loops Sink Chips. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:299-310 [Conf]
  6. R. Iris Bahar, Srilatha Manne
    Power and energy reduction via pipeline balancing. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:218-229 [Conf]
  7. Dirk Grunwald, Artur Klauser, Srilatha Manne, Andrew R. Pleszkun
    Confidence Estimation for Speculation Control. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:122-131 [Conf]
  8. Srilatha Manne, Artur Klauser, Dirk Grunwald
    Pipeline Gating: Speculation Control for Energy Reduction. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:132-141 [Conf]
  9. R. Iris Bahar, Gianluca Albera, Srilatha Manne
    Power and performance tradeoffs using various caching strategies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:64-69 [Conf]
  10. Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi
    CMOS dynamic power estimation based on collapsible current source transistor modeling. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:111-116 [Conf]
  11. Joel S. Emer, Pritpal Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan
    Asim: A Performance Model Framework. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:2, pp:68-76 [Journal]
  12. Artur Klauser, Srilatha Manne, Dirk Grunwald
    Selective Branch Inversion: Confidence Estimation for Branch Predictors. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2001, v:29, n:1, pp:81-110 [Journal]

  13. Accelerating two-dimensional page walks for virtualized systems. [Citation Graph (, )][DBLP]


  14. Perturbation-based Fault Screening. [Citation Graph (, )][DBLP]


Search in 0.021secs, Finished in 0.021secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002