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Jie-Hong Roland Jiang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jie-Hong Roland Jiang, Robert K. Brayton
    Functional Dependency for Verification Reduction. [Citation Graph (0, 0)][DBLP]
    CAV, 2004, pp:268-280 [Conf]
  2. Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang
    Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:712-717 [Conf]
  3. Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
    Reducing Multi-Valued Algebraic Operations to Binary. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10752-10757 [Conf]
  4. Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko
    Efficient Solution of Language Equations Using Partitioned Representations. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:418-423 [Conf]
  5. Jie-Hong Roland Jiang, Iris Hui-Ru Jiang
    Optimum loading dispersion for high-speed tree-type decision circuitry. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:520-525 [Conf]
  6. Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
    On breakable cyclic definitions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:411-418 [Conf]
  7. Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa
    Optimization of Multi-Valued Multi-Level Networks. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:168-0 [Conf]
  8. Jie-Hong Roland Jiang, Robert K. Brayton
    On the Verification of Sequential Equivalence. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:307-314 [Conf]
  9. Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
    Reducing Multi-Valued Algebraic Operations to Binary. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:339-344 [Conf]
  10. Jie-Hong Roland Jiang
    On Some Transformation Invariants Under Retiming and Resynthesis. [Citation Graph (0, 0)][DBLP]
    TACAS, 2005, pp:413-428 [Conf]
  11. Jie-Hong Roland Jiang, Robert K. Brayton
    On the verification of sequential equivalence. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:686-697 [Journal]
  12. Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang
    A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:148-159 [Conf]
  13. Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko
    Efficient Solution of Language Equations Using Partitioned Representations [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  14. Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang
    Unified functional decomposition via encoding for FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:251-260 [Journal]

  15. Bi-decomposing large Boolean functions via interpolation and satisfiability solving. [Citation Graph (, )][DBLP]


  16. Scalable don't-care-based logic optimization and resynthesis. [Citation Graph (, )][DBLP]


  17. Scalable exploration of functional dependency by interpolation and incremental SAT solving. [Citation Graph (, )][DBLP]


  18. Inductive equivalence checking under retiming and resynthesis. [Citation Graph (, )][DBLP]


  19. To SAT or not to SAT: Ashenhurst decomposition in a large scale. [Citation Graph (, )][DBLP]


  20. Interpolating functions from large Boolean relations. [Citation Graph (, )][DBLP]


  21. A dynamic accuracy-refinement approach to timing-driven technology mapping. [Citation Graph (, )][DBLP]


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