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Gjalt G. de Jong:
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- Gjalt G. de Jong
An Automata Theoretic Approach to Temporal Logic. [Citation Graph (0, 0)][DBLP] CAV, 1991, pp:477-487 [Conf]
- Mark Genoe, Christopher K. Lennard, Joachim Kunkel, Brian Bailey, Gjalt G. de Jong, Grant Martin, M. M. Kamal Hashmi, Shay Ben-Chorin, Anssi Haverinen
How standards will enable hardware/software co-design. [Citation Graph (0, 0)][DBLP] CODES, 1999, pp:211-212 [Conf]
- Gjalt G. de Jong, Bill Lin
A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules. [Citation Graph (0, 0)][DBLP] DAC, 1994, pp:49-55 [Conf]
- Bill Lin, Gjalt G. de Jong, Tilman Kolks
Hierarchical Optimization of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP] DAC, 1995, pp:712-717 [Conf]
- Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Miguel Miranda, Kris Croes, Sven Wuytack, Gjalt G. de Jong, Francky Catthoor, Diederik Verkest, Paul Six, Hugo De Man
Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer. [Citation Graph (0, 0)][DBLP] DAC, 1998, pp:76-81 [Conf]
- Eric Verlind, Gjalt G. de Jong, Bill Lin
Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems. [Citation Graph (0, 0)][DBLP] DAC, 1996, pp:55-58 [Conf]
- Eric Verlind, Tilman Kolks, Gjalt G. de Jong, Bill Lin, Hugo De Man
A Time Abstraction Method for Efficient Verification of Communicating Systems. [Citation Graph (0, 0)][DBLP] DAC, 1994, pp:609-614 [Conf]
- Daniel Gajski, Eugenio Villar, Wolfgang Rosenstiel, Vassilios Gerousis, D. Barton, J. Plantin, S. E. Ericsson, Patrizia Cavalloro, Gjalt G. de Jong
C/C++: progress or deadlock in system-level specification. [Citation Graph (0, 0)][DBLP] DATE, 2001, pp:136-137 [Conf]
- Gjalt G. de Jong
A UML-Based Design Methodology for Real-Time and Embedded Sytems. [Citation Graph (0, 0)][DBLP] DATE, 2002, pp:776-781 [Conf]
- Christopher K. Lennard, Patrick Schaumont, Gjalt G. de Jong, Anssi Haverinen, Pete Hardee
Standards for System-Level Design: Practical Reality or Solution in Search of a Question? [Citation Graph (0, 0)][DBLP] DATE, 2000, pp:576-0 [Conf]
- Alex Niemegeers, Gjalt G. de Jong
An Incremental Specification Flow for Real Time Embedded Systems. [Citation Graph (0, 0)][DBLP] DATE, 2000, pp:761- [Conf]
- Steven Vercauteren, Diederik Verkest, Gjalt G. de Jong, Bill Lin
Efficient Verification using Generalized Partial Order Analysis. [Citation Graph (0, 0)][DBLP] DATE, 1998, pp:782-789 [Conf]
- Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Bill Lin, Hugo De Man, Gjalt G. de Jong
A System Design Methodology for Telecommunication Network Applications. [Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1997, pp:64-69 [Conf]
- Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wuytack, Francky Catthoor
Background memory management for dynamic data structure intensive processing systems. [Citation Graph (0, 0)][DBLP] ICCAD, 1995, pp:515-520 [Conf]
- Peter Slock, Sven Wuytack, Francky Catthoor, Gjalt G. de Jong
Fast and Extensive System-Level Memory Exploration for ATM Applications. [Citation Graph (0, 0)][DBLP] ISSS, 1997, pp:74-81 [Conf]
- Steven Vercauteren, Diederik Verkest, Gjalt G. de Jong, Bill Lin
Derivation of Formal Representations from Process-Based Specification and Implementation Models. [Citation Graph (0, 0)][DBLP] ISSS, 1997, pp:16-0 [Conf]
- Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, Bill Lin, Hugo De Man
Flow Graph Balancing for Minimizing the Required Memory Bandwidth. [Citation Graph (0, 0)][DBLP] ISSS, 1996, pp:127-132 [Conf]
- Sven Wuytack, Julio Leao da Silva Jr., Francky Catthoor, Gjalt G. de Jong, Chantal Ykman-Couvreur
Memory management for embedded network applications. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:533-544 [Journal]
- Eric Verhulst, Gjalt G. de Jong
OpenComRTOS: An Ultra-Small Network Centric Embedded RTOS Designed Using Formal Modeling. [Citation Graph (0, 0)][DBLP] SDL Forum, 2007, pp:258-271 [Conf]
- Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, Hugo De Man
Minimizing the required memory bandwidth in VLSI system realizations. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1999, v:7, n:4, pp:433-441 [Journal]
Multi-thread graph: a system model for real-time embedded software synthesis. [Citation Graph (, )][DBLP]
An Industrial Case: Pitfalls and Benefits of Applying Formal Methods to the Development of a Network-Centric RTOS. [Citation Graph (, )][DBLP]
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