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Daher Kaiss: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss
    CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:131-143 [Conf]
  2. Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna
    Post-reboot Equivalence and Compositional Verification of Hardware. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:11-18 [Conf]
  3. Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna
    Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:58-65 [Conf]
  4. Nachum Dershowitz, Jieh Hsiang, Guan-Shieng Huang, Daher Kaiss
    Boolean Rings for Intersection-Based Satisfiability. [Citation Graph (0, 0)][DBLP]
    LPAR, 2006, pp:482-496 [Conf]
  5. Nachum Dershowitz, Jieh Hsiang, Guan-Shieng Huang, Daher Kaiss
    Boolean Ring Satisfiability. [Citation Graph (0, 0)][DBLP]
    SAT, 2004, pp:- [Conf]

  6. A compositional theory for post-reboot observational equivalence checking of hardware. [Citation Graph (, )][DBLP]


  7. Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification. [Citation Graph (, )][DBLP]


  8. Seqver : A Sequential Equivalence Verifier for Hardware Designs . [Citation Graph (, )][DBLP]


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