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John O'Leary: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. John O'Leary, Marly Roncken
    Rob Tristan Gerth: 1956?2003. [Citation Graph (0, 0)][DBLP]
    CAV, 2004, pp:1-14 [Conf]
  2. Michael Kishinevsky, Jordi Cortadella, Bill Grundmann, Sava Krstic, John O'Leary
    Synchronous Elastic Circuits. [Citation Graph (0, 0)][DBLP]
    CSR, 2006, pp:3-5 [Conf]
  3. Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi
    Formal verification - prove it or pitch it. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:710-711 [Conf]
  4. Sava Krstic, Jordi Cortadella, Michael Kishinevsky, John O'Leary
    Synchronous Elastic Networks. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:19-30 [Conf]
  5. Alan S. Wenban, Geoffrey Brown, John O'Leary
    Developing Interface Libraries for Reconfigurable Data Acquisition Boards. [Citation Graph (0, 0)][DBLP]
    FPL, 1995, pp:331-340 [Conf]
  6. Tevfik Bultan, Constance L. Heitmeyer, John O'Leary
    Panel on design for verification. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:232-235 [Conf]
  7. John O'Leary
    Formal verification in Intel CPU design. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2004, pp:152- [Conf]
  8. Alan S. Wenban, John O'Leary, Geoffrey Brown
    Codesign of Communication Protocols. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1993, v:26, n:12, pp:46-52 [Journal]
  9. Geoffrey Brown, Wayne Luk, John O'Leary
    Retargeting a Hardware Compiler Using Protokol Converters. [Citation Graph (0, 0)][DBLP]
    Formal Asp. Comput., 1996, v:8, n:2, pp:209-237 [Journal]
  10. John O'Leary, Geoffrey Brown, Wayne Luk
    Verified Compilation of Communicating Processes into Clocked Circuits. [Citation Graph (0, 0)][DBLP]
    Formal Asp. Comput., 1997, v:9, n:5-6, pp:537-559 [Journal]
  11. John O'Leary, Geoffrey Brown
    Synchronous emulation of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:2, pp:205-209 [Journal]
  12. Sava Krstic, Robert B. Jones, John O'Leary
    Mothers of Pipelines. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2007, v:174, n:8, pp:7-22 [Journal]
  13. Ganesh Gopalakrishnan, John O'Leary
    Preface. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2007, v:174, n:9, pp:1-4 [Journal]

  14. Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability. [Citation Graph (, )][DBLP]


  15. Static consistency checking for verilog wire interconnects: using dependent types to check the sanity of verilog descriptions. [Citation Graph (, )][DBLP]


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