The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Sumedh W. Sathaye: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte
    Path Prediction for High Issue-Rate Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1997, pp:178-188 [Conf]
  2. Emre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte
    A Fast Interrupt Handling Scheme for VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:136-141 [Conf]
  3. Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind
    Execution-Based Scheduling for VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:1269-1280 [Conf]
  4. Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye
    A technique to determine power-efficient, high-performance superscalar processors. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1995, pp:324-333 [Conf]
  5. Michael Gschwind, Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye
    Binary translation and architecture convergence issues for IBM system/390. [Citation Graph (0, 0)][DBLP]
    ICS, 2000, pp:336-347 [Conf]
  6. Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye
    Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:201-211 [Conf]
  7. Thomas M. Conte, Sumedh W. Sathaye
    Dynamic rescheduling: a technique for object code compatibility in VLIW architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:208-218 [Conf]
  8. Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia
    A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:4-13 [Conf]
  9. Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind
    Optimizations and Oracle Parallelism with Dynamic Translation. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:284-0 [Conf]
  10. Michael Gschwind, Erik R. Altman, Sumedh W. Sathaye, Paul Ledak, David Appenzeller
    Dynamic and Transparent Binary Translation. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2000, v:33, n:3, pp:54-59 [Journal]
  11. Erik R. Altman, Sumedh W. Sathaye
    Preface. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2006, v:50, n:2-3, pp:169-171 [Journal]
  12. Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte
    MPS: Miss-Path Scheduling for Multiple-Issue Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:12, pp:1382-1397 [Journal]
  13. Thomas M. Conte, Sumedh W. Sathaye
    Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:8, pp:814-825 [Journal]
  14. Kemal Ebcioglu, Erik R. Altman, Michael Gschwind, Sumedh W. Sathaye
    Dynamic Binary Translation and Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:6, pp:529-548 [Journal]
  15. Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen
    System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:129-137 [Journal]

Search in 0.016secs, Finished in 0.017secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002