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Manish Pandey: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Manish Pandey, Randal E. Bryant
    Exploiting Symmetry When Verifying Transitor-Level Circuits by Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    CAV, 1997, pp:244-255 [Conf]
  2. Manish Pandey, Richard Raimi, Randal E. Bryant, Magdy S. Abadir
    Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:167-172 [Conf]
  3. Manish Pandey, Richard Raimi, Derek L. Beatty, Randal E. Bryant
    Formal Verification of PowerPC Arrays Using Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:649-654 [Conf]
  4. Manish Pandey, Alok Jain, Randal E. Bryant, Derek L. Beatty, Gary York, Samir Jain
    Extraction of finite state machines from transistor netlists by symbolic simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:596-601 [Conf]
  5. Neeta Ganguly, Magdy S. Abadir, Manish Pandey
    PowerPCTM Array Verification Methodology using Formal Techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:857-864 [Conf]
  6. Manish Pandey, Randal E. Bryant
    Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:918-935 [Journal]

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