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Michael C. Huang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Francisco J. Mesa-Martinez, Michael C. Huang, Jose Renau
    SEED: scalable, efficient enforcement of dependences. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:254-264 [Conf]
  2. M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi
    Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:315-328 [Conf]
  3. Jian Li, José F. Martínez, Michael C. Huang
    The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:14-23 [Conf]
  4. Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang
    Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism.. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:617-624 [Conf]
  5. Wei Liu, Michael C. Huang
    EXPERT: expedited simulation exploiting program behavior repetition. [Citation Graph (0, 0)][DBLP]
    ICS, 2004, pp:126-135 [Conf]
  6. Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
    Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:152-159 [Conf]
  7. Chen Ding, Sandhya Dwarkadas, Michael C. Huang, Kai Shen, J. B. Carter
    Program phase detection and exploitation. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  8. Alok Garg, M. Wasiur Rashid, Michael C. Huang
    Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:142-154 [Conf]
  9. Michael C. Huang, Jose Renau, Josep Torrellas
    Positional Adaptation of Processors: Application to Energy Reduction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:157-168 [Conf]
  10. Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang
    Branch prediction on demand: an energy-efficient solution. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:390-395 [Conf]
  11. Daniel Chaver, Miguel A. Rojas, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang
    Energy-aware fetch mechanism: trace cache and BTB customization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:42-47 [Conf]
  12. Michael C. Huang, Jose Renau, Josep Torrellas
    Energy-efficient hybrid wakeup logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:196-201 [Conf]
  13. Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
    L1 data cache decomposition for energy efficiency. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:10-15 [Conf]
  14. Alok Garg, Fernando Castro, Michael C. Huang, Daniel Chaver, Luis Piñuel, Manuel Prieto
    Substituting associative load queue with simple hash tables in out-of-order microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:268-273 [Conf]
  15. Liem Tran, Nicholas Nelson, Fung Ngai, Steve Dropsho, Michael C. Huang
    Dynamically reducing pressure on the physical register file through simple register sharing. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2004, pp:78-87 [Conf]
  16. Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
    A framework for dynamic energy efficiency and temperature management. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:202-213 [Conf]
  17. José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas
    Cherry: checkpointed early resource recycling in out-of-order microprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:3-14 [Conf]
  18. Fernando Castro, Luis Piñuel, Daniel Chaver, Manuel Prieto, Michael C. Huang, Francisco Tirado
    DMDC: Delayed Memory Dependence Checking through Age-Based Filtering. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:297-308 [Conf]
  19. Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Michael C. Huang, Francisco Tirado
    A Power-Efficient and Scalable Load-Store Queue Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:1-9 [Conf]
  20. David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster
    Dynamically Tuning Processor Resources with Adaptive Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:12, pp:49-58 [Journal]
  21. Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
    The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2001, v:3, n:, pp:- [Journal]
  22. Michael C. Huang, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado
    Customizing the Branch Predictor to Reduce Complexity and Energy Consumption. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:5, pp:12-25 [Journal]
  23. M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi
    Power-Efficient Error Tolerance in Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:6, pp:60-70 [Journal]
  24. Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Michael C. Huang, Francisco Tirado
    A Load-Store Queue Design Based on Predictive State Filtering. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:27-36 [Journal]

  25. DDCache: Decoupled and Delegable Cache Data and Metadata. [Citation Graph (, )][DBLP]


  26. Improving support for locality and fine-grain sharing in chip multiprocessors. [Citation Graph (, )][DBLP]


  27. Topic 4: High Performance Architectures and Compilers. [Citation Graph (, )][DBLP]


  28. Supporting highly-decoupled thread-level redundancy for parallel programs. [Citation Graph (, )][DBLP]


  29. Software-hardware cooperative memory disambiguation. [Citation Graph (, )][DBLP]


  30. An intra-chip free-space optical interconnect. [Citation Graph (, )][DBLP]


  31. Variation-tolerant hierarchical voltage monitoring circuit for soft error detection. [Citation Graph (, )][DBLP]


  32. A performance-correctness explicitly-decoupled architecture. [Citation Graph (, )][DBLP]


  33. A Memory Soft Error Measurement on Production Systems. [Citation Graph (, )][DBLP]


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