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Poul Frederick Williams: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Poul Frederick Williams, Armin Biere, Edmund M. Clarke, Anubhav Gupta
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
CAV, 2000, pp:124-138 [Conf] - Poul Frederick Williams, Henrik Reif Andersen, Henrik Hulgaard
Satisfiability Checking Using Boolean Expression Diagrams. [Citation Graph (0, 0)][DBLP]
TACAS, 2001, pp:39-51 [Conf] - Poul Frederick Williams
Formal Verification based on Boolean Expression Diagrams. [Citation Graph (0, 0)][DBLP]
Electr. Notes Theor. Comput. Sci., 2001, v:56, n:, pp:- [Journal] - Poul Frederick Williams, Macha Nikolskaïa, Antoine Rauzy
Bypassing BDD construction for reliability analysis. [Citation Graph (0, 0)][DBLP]
Inf. Process. Lett., 2000, v:75, n:1-2, pp:85-89 [Journal] - Poul Frederick Williams, Henrik Reif Andersen, Henrik Hulgaard
Satisfiability checking using Boolean Expression Diagrams. [Citation Graph (0, 0)][DBLP]
STTT, 2003, v:5, n:1, pp:4-14 [Journal] - Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen
Equivalence checking of combinational circuits using Boolean expression diagrams. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:903-917 [Journal]
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