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Jose Renau:
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Publications of Author
- Francisco J. Mesa-Martinez, Michael C. Huang, Jose Renau
SEED: scalable, efficient enforcement of dependences. [Citation Graph (0, 0)][DBLP] PACT, 2006, pp:254-264 [Conf]
- Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas
Thread-Level Speculation on a CMP can be energy efficient. [Citation Graph (0, 0)][DBLP] ICS, 2005, pp:219-228 [Conf]
- Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation. [Citation Graph (0, 0)][DBLP] ICS, 2005, pp:179-188 [Conf]
- Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. [Citation Graph (0, 0)][DBLP] Intelligent Memory Systems, 2000, pp:152-159 [Conf]
- Michael C. Huang, Jose Renau, Josep Torrellas
Positional Adaptation of Processors: Application to Energy Reduction. [Citation Graph (0, 0)][DBLP] ISCA, 2003, pp:157-168 [Conf]
- Michael C. Huang, Jose Renau, Josep Torrellas
Energy-efficient hybrid wakeup logic. [Citation Graph (0, 0)][DBLP] ISLPED, 2002, pp:196-201 [Conf]
- Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
L1 data cache decomposition for energy efficiency. [Citation Graph (0, 0)][DBLP] ISLPED, 2001, pp:10-15 [Conf]
- Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau
uComplexity: Estimating Processor Design Effort. [Citation Graph (0, 0)][DBLP] MICRO, 2005, pp:209-218 [Conf]
- Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
A framework for dynamic energy efficiency and temperature management. [Citation Graph (0, 0)][DBLP] MICRO, 2000, pp:202-213 [Conf]
- José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas
Cherry: checkpointed early resource recycling in out-of-order microprocessors. [Citation Graph (0, 0)][DBLP] MICRO, 2002, pp:3-14 [Conf]
- Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas
Programming the FlexRAM parallel intelligent memory system. [Citation Graph (0, 0)][DBLP] PPOPP, 2003, pp:49-60 [Conf]
- Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas
POSH: a TLS compiler that exploits program structure. [Citation Graph (0, 0)][DBLP] PPOPP, 2006, pp:158-167 [Conf]
- Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management. [Citation Graph (0, 0)][DBLP] J. Instruction-Level Parallelism, 2001, v:3, n:, pp:- [Journal]
- Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas
Energy-Efficient Thread-Level Speculation. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2006, v:26, n:1, pp:80-91 [Journal]
- Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau
CAVA: Using checkpoint-assisted value prediction to hide L2 misses. [Citation Graph (0, 0)][DBLP] TACO, 2006, v:3, n:2, pp:182-208 [Journal]
- Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau
Power model validation through thermal measurements. [Citation Graph (0, 0)][DBLP] ISCA, 2007, pp:302-311 [Conf]
Characterizing processor thermal behavior. [Citation Graph (, )][DBLP]
Measuring and modeling variabilityusing low-cost FPGAs. [Citation Graph (, )][DBLP]
Measuring power and temperature from real processors. [Citation Graph (, )][DBLP]
SOI, interconnect, package, and mainboard thermal characterization. [Citation Graph (, )][DBLP]
Processor Verification with hwBugHunt. [Citation Graph (, )][DBLP]
Effective Optimistic-Checker Tandem Core Design through Architectural Pruning. [Citation Graph (, )][DBLP]
Understanding bug fix patterns in verilog. [Citation Graph (, )][DBLP]
Estimating design time for system circuits. [Citation Graph (, )][DBLP]
Measuring performance, power, and temperature from real processors. [Citation Graph (, )][DBLP]
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