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Stéphan Jourdan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pierre Michaud, André Seznec, Stéphan Jourdan
    Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:2-10 [Conf]
  2. Robert Cooksey, Stéphan Jourdan, Dirk Grunwald
    A stateless, content-directed data prefetching mechanism. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:279-290 [Conf]
  3. André Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud
    Multiple-Block Ahead Branch Predictors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1996, pp:116-127 [Conf]
  4. Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen
    eXtended Block Cache. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:61-0 [Conf]
  5. Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stéphan Jourdan, Maxim Kalaev, Ronny Ronen
    Early load address resolution via register tracking. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:306-315 [Conf]
  6. Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri Weiser
    Correlated Load-Address Predictors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:54-63 [Conf]
  7. Stéphan Jourdan, Pascal Sainrat, Daniel Litaize
    Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:117-125 [Conf]
  8. Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan Jourdan
    Speculation Techniques for Improving Load Related Instruction Scheduling. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:42-53 [Conf]
  9. Stéphan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz
    A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:216-225 [Conf]
  10. Stéphan Jourdan, Pascal Sainrat, Daniel Litaize
    An investigation of the performance of various instruction-issue buffer topologies. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:279-284 [Conf]
  11. Pierre Michaud, André Seznec, Stéphan Jourdan
    An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2001, v:29, n:1, pp:35-58 [Journal]

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