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Enric Morancho: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Enric Morancho, José María Llabería, Àngel Olivé
    Recovery Mechanism for Latency Misprediction. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:118-0 [Conf]
  2. Enric Morancho, José M. Llabería, Àngel Olivé
    Split Last-Address Predictor. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:230-0 [Conf]
  3. Enric Morancho, José M. Llabería, Àngel Olivé
    Looking at History to Filter Allocations in Prediction Tables. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:314-319 [Conf]
  4. Javier Larrosa, Enric Morancho
    Solving 'Still Life' with Soft Constraints and Bucket Elimination. [Citation Graph (0, 0)][DBLP]
    CP, 2003, pp:466-479 [Conf]
  5. Marta Jiménez, José M. Llabería, Agustin Fernández, Enric Morancho
    A Unified Transformation Technique for Multilevel Blocking. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. I, 1996, pp:402-405 [Conf]
  6. Enric Morancho, José M. Llabería, Àngel Olivé
    Two-Level Address Storage and Address Prediction (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:960-964 [Conf]
  7. Enric Morancho, José María Llabería, Àngel Olivé
    A Mechanism for Verifying Data Speculation. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:525-534 [Conf]
  8. Marta Jiménez, José M. Llabería, Agustin Fernández, Enric Morancho
    A General Algorithm for Tiling the Register Level. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:133-140 [Conf]
  9. Enric Morancho, José María Llabería, Àngel Olivé
    A comparison of two policies for issuing instructions speculatively. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:4, pp:170-183 [Journal]
  10. Javier Larrosa, Enric Morancho, David Niso
    On the Practical use of Variable Elimination in Constraint Optimization Problems: 'Still-life' as a Case Study. [Citation Graph (0, 0)][DBLP]
    J. Artif. Intell. Res. (JAIR), 2005, v:23, n:, pp:421-440 [Journal]

  11. An Enhancement for a Scheduling Logic Pipelined over two Cycles . [Citation Graph (, )][DBLP]


  12. On reducing misspeculations in a pipelined scheduler. [Citation Graph (, )][DBLP]


  13. On reducing energy-consumption by late-inserting instructions into the issue queue. [Citation Graph (, )][DBLP]


  14. High-Performance Reverse Time Migration on GPU. [Citation Graph (, )][DBLP]


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