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Andreas Moshovos:
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Publications of Author
- Andreas Moshovos, Alexandros Kostopoulos
Memory State Compressors for Giga-Scale Checkpoint/Restore. [Citation Graph (0, 0)][DBLP] IEEE PACT, 2005, pp:303-314 [Conf]
- Amir Roth, Andreas Moshovos, Gurindar S. Sohi
Dependance Based Prefetching for Linked Data Structures. [Citation Graph (0, 0)][DBLP] ASPLOS, 1998, pp:115-126 [Conf]
- Chi F. Chen, Se-Hyun Yang, Babak Falsafi, Andreas Moshovos
Accurate and Complexity-Effective Spatial Pattern Prediction. [Citation Graph (0, 0)][DBLP] HPCA, 2004, pp:276-287 [Conf]
- Andreas Moshovos, Gokhan Memik, Babak Falsafi, Alok N. Choudhary
JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers. [Citation Graph (0, 0)][DBLP] HPCA, 2001, pp:85-96 [Conf]
- Andreas Moshovos, Gurindar S. Sohi
Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. [Citation Graph (0, 0)][DBLP] HPCA, 2000, pp:301-312 [Conf]
- Amirali Baniasadi, Andreas Moshovos
Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors. [Citation Graph (0, 0)][DBLP] ICCD, 2002, pp:458-461 [Conf]
- Won-Ho Park, Andreas Moshovos, Babak Falsafi
RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free". [Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:609-616 [Conf]
- Andreas Moshovos, Dionisios N. Pnevmatikatos, Amirali Baniasadi
Slice-processors: an implementation of operation-based prediction. [Citation Graph (0, 0)][DBLP] ICS, 2001, pp:321-334 [Conf]
- Amir Roth, Andreas Moshovos, Gurindar S. Sohi
Improving virtual function call target prediction via dependence-based pre-computation. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1999, pp:356-364 [Conf]
- Patrick Akl, Andreas Moshovos
BranchTap: improving performance with very few checkpoints through adaptive speculation control. [Citation Graph (0, 0)][DBLP] ICS, 2006, pp:36-45 [Conf]
- Andreas Moshovos
RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence. [Citation Graph (0, 0)][DBLP] ISCA, 2005, pp:234-245 [Conf]
- Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi
Dynamic Speculation and Synchronization of Data Dependences. [Citation Graph (0, 0)][DBLP] ISCA, 1997, pp:181-193 [Conf]
- Stephen Somogyi, Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos
Spatial Memory Streaming. [Citation Graph (0, 0)][DBLP] ISCA, 2006, pp:252-263 [Conf]
- Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. [Citation Graph (0, 0)][DBLP] ISCA, 2000, pp:225-235 [Conf]
- Navid Azizi, Andreas Moshovos, Farid N. Najm
Low-leakage asymmetric-cell SRAM. [Citation Graph (0, 0)][DBLP] ISLPED, 2002, pp:48-51 [Conf]
- Amirali Baniasadi, Andreas Moshovos
Instruction flow-based front-end throttling for power-aware high-performance processors. [Citation Graph (0, 0)][DBLP] ISLPED, 2001, pp:16-21 [Conf]
- Amirali Baniasadi, Andreas Moshovos
Asymmetric-frequency clustering: a power-aware back-end for high-performance processors. [Citation Graph (0, 0)][DBLP] ISLPED, 2002, pp:255-258 [Conf]
- Amirali Baniasadi, Andreas Moshovos
SEPAS: a highly accurate energy-efficient branch predictor. [Citation Graph (0, 0)][DBLP] ISLPED, 2004, pp:38-43 [Conf]
- Andreas Moshovos
Checkpointing alternatives for high performance, power-aware processors. [Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:318-321 [Conf]
- Elham Safi, Andreas Moshovos, Andreas G. Veneris
L-CBF: a low-power, fast counting bloom filter architecture. [Citation Graph (0, 0)][DBLP] ISLPED, 2006, pp:250-255 [Conf]
- Amirali Baniasadi, Andreas Moshovos
Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors. [Citation Graph (0, 0)][DBLP] MICRO, 2000, pp:337-347 [Conf]
- Andreas Moshovos, Gurindar S. Sohi
Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. [Citation Graph (0, 0)][DBLP] MICRO, 1997, pp:235-245 [Conf]
- Andreas Moshovos, Gurindar S. Sohi
Read-After-Read Memory Dependence Prediction. [Citation Graph (0, 0)][DBLP] MICRO, 1999, pp:177-185 [Conf]
- Ahmed Abdelkhalek, Angelos Bilas, Andreas Moshovos
Behavior and Performance of Interactive Multi-Player Game Servers. [Citation Graph (0, 0)][DBLP] Cluster Computing, 2003, v:6, n:4, pp:355-366 [Journal]
- Andreas Moshovos, Gurindar S. Sohi
Speculative Memory Cloaking and Bypassing. [Citation Graph (0, 0)][DBLP] International Journal of Parallel Programming, 1999, v:27, n:6, pp:427-456 [Journal]
- Andreas Moshovos, Gurindar S. Sohi
Memory Dependence Prediction in Multimedia Applications. [Citation Graph (0, 0)][DBLP] J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
- Jason F. Cantin, James E. Smith, Mikko H. Lipasti, Andreas Moshovos, Babak Falsafi
Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2006, v:26, n:1, pp:70-79 [Journal]
- Andreas Moshovos, Gurindar S. Sohi
Reducing Memory Latency via Read-after-Read Memory Dependence Prediction. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2002, v:51, n:3, pp:313-326 [Journal]
- Andreas Moshovos, Babak Falsafi, Farid N. Najm, Navid Azizi
A Case for Asymmetric-Cell Cache Memories. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:7, pp:877-881 [Journal]
- Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos
Mechanisms for store-wait-free multiprocessors. [Citation Graph (0, 0)][DBLP] ISCA, 2007, pp:266-277 [Conf]
- Navid Azizi, Farid N. Najm, Andreas Moshovos
Low-leakage asymmetric-cell SRAM. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:701-715 [Journal]
Predictor virtualization. [Citation Graph (, )][DBLP]
Phantom-BTB: a virtualized branch target buffer design. [Citation Graph (, )][DBLP]
Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming. [Citation Graph (, )][DBLP]
Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator. [Citation Graph (, )][DBLP]
Practical off-chip meta-data for temporal memory streaming. [Citation Graph (, )][DBLP]
A physical level study and optimization of CAM-based checkpointed register alias table. [Citation Graph (, )][DBLP]
On the latency, energy and area of checkpointed, superscalar register alias tables. [Citation Graph (, )][DBLP]
Demystifying GPU microarchitecture through microbenchmarking. [Citation Graph (, )][DBLP]
Temporal instruction fetch streaming. [Citation Graph (, )][DBLP]
A tagless coherence directory. [Citation Graph (, )][DBLP]
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. [Citation Graph (, )][DBLP]
A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. [Citation Graph (, )][DBLP]
Temporal streams in commercial server applications. [Citation Graph (, )][DBLP]
A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. [Citation Graph (, )][DBLP]
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