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Andreas Moshovos: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andreas Moshovos, Alexandros Kostopoulos
    Memory State Compressors for Giga-Scale Checkpoint/Restore. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:303-314 [Conf]
  2. Amir Roth, Andreas Moshovos, Gurindar S. Sohi
    Dependance Based Prefetching for Linked Data Structures. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1998, pp:115-126 [Conf]
  3. Chi F. Chen, Se-Hyun Yang, Babak Falsafi, Andreas Moshovos
    Accurate and Complexity-Effective Spatial Pattern Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:276-287 [Conf]
  4. Andreas Moshovos, Gokhan Memik, Babak Falsafi, Alok N. Choudhary
    JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:85-96 [Conf]
  5. Andreas Moshovos, Gurindar S. Sohi
    Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:301-312 [Conf]
  6. Amirali Baniasadi, Andreas Moshovos
    Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:458-461 [Conf]
  7. Won-Ho Park, Andreas Moshovos, Babak Falsafi
    RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free". [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:609-616 [Conf]
  8. Andreas Moshovos, Dionisios N. Pnevmatikatos, Amirali Baniasadi
    Slice-processors: an implementation of operation-based prediction. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:321-334 [Conf]
  9. Amir Roth, Andreas Moshovos, Gurindar S. Sohi
    Improving virtual function call target prediction via dependence-based pre-computation. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:356-364 [Conf]
  10. Patrick Akl, Andreas Moshovos
    BranchTap: improving performance with very few checkpoints through adaptive speculation control. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:36-45 [Conf]
  11. Andreas Moshovos
    RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:234-245 [Conf]
  12. Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi
    Dynamic Speculation and Synchronization of Data Dependences. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:181-193 [Conf]
  13. Stephen Somogyi, Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos
    Spatial Memory Streaming. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:252-263 [Conf]
  14. Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee
    CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:225-235 [Conf]
  15. Navid Azizi, Andreas Moshovos, Farid N. Najm
    Low-leakage asymmetric-cell SRAM. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:48-51 [Conf]
  16. Amirali Baniasadi, Andreas Moshovos
    Instruction flow-based front-end throttling for power-aware high-performance processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:16-21 [Conf]
  17. Amirali Baniasadi, Andreas Moshovos
    Asymmetric-frequency clustering: a power-aware back-end for high-performance processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:255-258 [Conf]
  18. Amirali Baniasadi, Andreas Moshovos
    SEPAS: a highly accurate energy-efficient branch predictor. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:38-43 [Conf]
  19. Andreas Moshovos
    Checkpointing alternatives for high performance, power-aware processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:318-321 [Conf]
  20. Elham Safi, Andreas Moshovos, Andreas G. Veneris
    L-CBF: a low-power, fast counting bloom filter architecture. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:250-255 [Conf]
  21. Amirali Baniasadi, Andreas Moshovos
    Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:337-347 [Conf]
  22. Andreas Moshovos, Gurindar S. Sohi
    Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:235-245 [Conf]
  23. Andreas Moshovos, Gurindar S. Sohi
    Read-After-Read Memory Dependence Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:177-185 [Conf]
  24. Ahmed Abdelkhalek, Angelos Bilas, Andreas Moshovos
    Behavior and Performance of Interactive Multi-Player Game Servers. [Citation Graph (0, 0)][DBLP]
    Cluster Computing, 2003, v:6, n:4, pp:355-366 [Journal]
  25. Andreas Moshovos, Gurindar S. Sohi
    Speculative Memory Cloaking and Bypassing. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:6, pp:427-456 [Journal]
  26. Andreas Moshovos, Gurindar S. Sohi
    Memory Dependence Prediction in Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  27. Jason F. Cantin, James E. Smith, Mikko H. Lipasti, Andreas Moshovos, Babak Falsafi
    Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:70-79 [Journal]
  28. Andreas Moshovos, Gurindar S. Sohi
    Reducing Memory Latency via Read-after-Read Memory Dependence Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:3, pp:313-326 [Journal]
  29. Andreas Moshovos, Babak Falsafi, Farid N. Najm, Navid Azizi
    A Case for Asymmetric-Cell Cache Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:7, pp:877-881 [Journal]
  30. Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos
    Mechanisms for store-wait-free multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:266-277 [Conf]
  31. Navid Azizi, Farid N. Najm, Andreas Moshovos
    Low-leakage asymmetric-cell SRAM. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:701-715 [Journal]

  32. Predictor virtualization. [Citation Graph (, )][DBLP]


  33. Phantom-BTB: a virtualized branch target buffer design. [Citation Graph (, )][DBLP]


  34. Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming. [Citation Graph (, )][DBLP]


  35. Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator. [Citation Graph (, )][DBLP]


  36. Practical off-chip meta-data for temporal memory streaming. [Citation Graph (, )][DBLP]


  37. A physical level study and optimization of CAM-based checkpointed register alias table. [Citation Graph (, )][DBLP]


  38. On the latency, energy and area of checkpointed, superscalar register alias tables. [Citation Graph (, )][DBLP]


  39. Demystifying GPU microarchitecture through microbenchmarking. [Citation Graph (, )][DBLP]


  40. Temporal instruction fetch streaming. [Citation Graph (, )][DBLP]


  41. A tagless coherence directory. [Citation Graph (, )][DBLP]


  42. A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. [Citation Graph (, )][DBLP]


  43. A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. [Citation Graph (, )][DBLP]


  44. Temporal streams in commercial server applications. [Citation Graph (, )][DBLP]


  45. A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. [Citation Graph (, )][DBLP]


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