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Edwin Naroska: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Edwin Naroska, Rung-Ji Shang, Feipei Lai, Uwe Schwiegelshohn
    Hybrid Parallel Circuit Simulation Approaches. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:261-270 [Conf]
  2. Jörg Platte, Edwin Naroska, Kai Grundmann
    A Cache Design for a Security Architecture for Microprocessors (SAM). [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:435-449 [Conf]
  3. Jörg Platte, Edwin Naroska
    A combined hardware and software architecture for secure computing. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:280-288 [Conf]
  4. Jörg Platte, Raúl Durán Díaz, Edwin Naroska
    A New Encryption and Hashing Scheme for the Security Architecture for Microprocessors. [Citation Graph (0, 0)][DBLP]
    Communications and Multimedia Security, 2006, pp:120-129 [Conf]
  5. Edwin Naroska
    Parallel VHDL Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:159-0 [Conf]
  6. Edwin Naroska, Uwe Schwiegelshohn
    A New Scheduling Method for Parallel Discrete-Event Simulation. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. II, 1996, pp:582-593 [Conf]
  7. Uwe Schwiegelshohn, Edwin Naroska
    Verlustleistungsarme Fehlerschutzprotokolle basierend auf punktierten Low Density Parity Check Codes (LDPC). [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:461- [Conf]
  8. Shanq-Jang Ruan, Edwin Naroska, Chia-Lin Ho, Feipei Lai
    Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:327-0 [Conf]
  9. Jörg Platte, Raúl Durán Díaz, Edwin Naroska
    An Operating System Design for the Security Architecture for Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICICS, 2006, pp:174-189 [Conf]
  10. Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn
    Simultaneous Wire Permutation, Inversion, and Spacing with Genetic Algorithm for Energy-Efficient Bus Design. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  11. Edwin Naroska, Shanq-Jang Ruan, Feipei Lai, Uwe Schwiegelshohn, Le-Chin Liu
    On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:277-280 [Conf]
  12. Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn
    An efficient algorithm for simultaneous wire permutation, inversion, and spacing. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:109-112 [Conf]
  13. Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen
    Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:114-119 [Conf]
  14. Edwin Naroska, Uwe Schwiegelshohn
    On an on-line scheduling problem for parallel jobs. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2002, v:81, n:6, pp:297-304 [Journal]
  15. Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai
    Bipartitioning and encoding in low-power pipelined circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:24-32 [Journal]
  16. Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn
    Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:421-425 [Journal]
  17. Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn
    ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:942-949 [Journal]

  18. Structured Learning of Component Dependencies in AmI Systems. [Citation Graph (, )][DBLP]


  19. „inBath“ – assistive Badumgebung. [Citation Graph (, )][DBLP]


  20. A probabilistic reasoning framework for smart homes. [Citation Graph (, )][DBLP]


  21. Unsupervised Recognition of ADLs. [Citation Graph (, )][DBLP]


  22. Energy analysis of bipartition architecture for pipelined circuits. [Citation Graph (, )][DBLP]


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