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James E. Smith: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kyle J. Nesbit, Ashutosh S. Dhodapkar, James E. Smith
    AC/DC: An Adaptive Data Cache Prefetcher. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:135-145 [Conf]
  2. Sébastien Nussbaum, James E. Smith
    Modeling Superscalar Processors via Statistical Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:15-24 [Conf]
  3. James E. Smith
    Some Real Observations on Virtual Machines. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2004, pp:1- [Conf]
  4. Sébastien Nussbaum, James E. Smith
    Statistical Simulation of Symmetric Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 2002, pp:89-97 [Conf]
  5. James E. Smith, G. E. Dermer, B. D. Vanderwarn, S. D. Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, James Laudon
    The ZS-1 Central Processor. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1987, pp:199-204 [Conf]
  6. Shlomo Weiss, James E. Smith
    A Study of Scalar Compilation Techniques for Pipelined Supercomputers. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1987, pp:105-109 [Conf]
  7. Jason F. Cantin, Mikko H. Lipasti, James E. Smith
    Stealth prefetching. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:274-282 [Conf]
  8. Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith
    A performance counter architecture for computing accurate CPI components. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:175-184 [Conf]
  9. Franz A. Pertl, Andrew D. Lowery, James E. Smith
    Numerical Wire Grid Modeling of Cavity Resonators to determine Quality Factors. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2006, pp:188-191 [Conf]
  10. Ramon Canal, Antonio González, James E. Smith
    Software-Controlled Operand-Gating. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:125-136 [Conf]
  11. Kim M. Hazelwood, James E. Smith
    Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:89-99 [Conf]
  12. Shiliang Hu, James E. Smith
    Using Dynamic Binary Translation to Fuse Dependent Instructions. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:213-226 [Conf]
  13. Ho-Seop Kim, James E. Smith
    Dynamic Binary Translation for Accumulator-Oriented Architectures. [Citation Graph (0, 0)][DBLP]
    CGO, 2003, pp:25-35 [Conf]
  14. Ramon Canal, Antonio González, James E. Smith
    Value Compression for Efficient Computation. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2005, pp:519-529 [Conf]
  15. James E. Smith
    Instruction Level Distributed Processing. [Citation Graph (0, 0)][DBLP]
    HiPC, 2000, pp:245-258 [Conf]
  16. Quinn Jacobson, Steve Bennett, Nikhil Sharma, James E. Smith
    Control Flow Speculation in Multiscalar Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:218-229 [Conf]
  17. Quinn Jacobson, James E. Smith
    Instruction Pre-Processing in Trace Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:125-129 [Conf]
  18. Sridhar Gopal, T. N. Vijaykumar, James E. Smith, Gurindar S. Sohi
    Speculative Versioning Cache. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:195-205 [Conf]
  19. Kyle J. Nesbit, James E. Smith
    Data Cache Prefetching Using a Global History Buffer. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:96-105 [Conf]
  20. Eric Rotenberg, Quinn Jacobson, James E. Smith
    A Study of Control Independence in Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:115-124 [Conf]
  21. Steven R. Kunkel, James E. Smith
    Pipelined Register-Storage Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:515-518 [Conf]
  22. Juan L. Aragón, José González, Antonio González, James E. Smith
    Dual path instruction processing. [Citation Graph (0, 0)][DBLP]
    ICS, 2002, pp:220-229 [Conf]
  23. Roger Espasa, Mateo Valero, James E. Smith
    Vector Architectures: Past, Present and Future. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:425-432 [Conf]
  24. James E. Smith
    Keynote: Is there anything more to learn about high performance processors? [Citation Graph (0, 0)][DBLP]
    ICS, 2003, pp:75- [Conf]
  25. Gurindar S. Sohi, James E. Smith, James R. Goodman
    Restricted Fetch&Phi operations for parallel processing. [Citation Graph (0, 0)][DBLP]
    ICS, 1989, pp:410-416 [Conf]
  26. Ashutosh S. Dhodapkar, James E. Smith
    Tuning Reconfigurable Microarchitectures for Power Efficiency. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  27. Shiliang Hu, James E. Smith
    Reducing Startup Time in Co-Designed Virtual Machines. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:277-288 [Conf]
  28. Jason F. Cantin, Mikko H. Lipasti, James E. Smith
    Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:246-257 [Conf]
  29. Ashutosh S. Dhodapkar, James E. Smith
    Managing Multi-Configuration Hardware via Dynamic Working Set Analysis. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:233-0 [Conf]
  30. Wei-Chung Hsu, James E. Smith
    Performance of Cached DRAM Organizations in Vector Supercomputers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:327-336 [Conf]
  31. Quinn Jacobson, James E. Smith
    Trace preconstruction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:37-46 [Conf]
  32. Tejas Karkhanis, James E. Smith
    A First-Order Superscalar Processor Model. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:338-349 [Conf]
  33. Ho-Seop Kim, James E. Smith
    An Instruction Set and Microarchitecture for Instruction Level Distributed Processing. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:71-0 [Conf]
  34. Steven R. Kunkel, James E. Smith
    Optimal Pipelining in Supercomputers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:404-411 [Conf]
  35. Subbarao Palacharla, Norman P. Jouppi, James E. Smith
    Complexity-Effective Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:206-218 [Conf]
  36. S. Subramanya Sastry, Rastislav Bodík, James E. Smith
    Rapid profiling via stratified sampling. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:278-289 [Conf]
  37. Yiannakis Sazeides, James E. Smith
    Modeling Program Predictability. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:73-84 [Conf]
  38. James E. Smith
    A Study of Branch Prediction Strategies. [Citation Graph (0, 0)][DBLP]
    ISCA, 1981, pp:135-148 [Conf]
  39. James E. Smith
    Decoupled access/execute computer architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1982, pp:112-119 [Conf]
  40. James E. Smith
    Retrospective: A Study of Branch Prediction Strategies. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:22-23 [Conf]
  41. James E. Smith
    Retrospective: Decoupled Access/Execute Architectures. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:27-28 [Conf]
  42. James E. Smith
    Retrospective: Implementing Precise Interrupts in Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:42- [Conf]
  43. James E. Smith
    A Study of Branch Prediction Strategies. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:202-215 [Conf]
  44. James E. Smith
    Decoupled Access/Execute Computer Architectures. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:231-238 [Conf]
  45. James E. Smith, Greg Faanes, Rabin A. Sugumar
    Vector instruction set support for conditional operations. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:260-269 [Conf]
  46. James E. Smith, James R. Goodman
    A Study of Instruction Cache Organizations and Replacement Policies [Citation Graph (0, 0)][DBLP]
    ISCA, 1983, pp:132-137 [Conf]
  47. James E. Smith, Andrew R. Pleszkun
    Implementation of Precise Interrupts in Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:36-44 [Conf]
  48. James E. Smith, Andrew R. Pleszkun
    Implementation of Precise Interupts in Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:291-299 [Conf]
  49. Shlomo Weiss, James E. Smith
    Instruction Issue Logic for Pipelined Supercomputers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1984, pp:110-118 [Conf]
  50. James E. Smith
    Instruction Level Distributed Processing: Adapting to Future Technology. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2000, pp:1-6 [Conf]
  51. Tejas Karkhanis, James E. Smith, Pradip Bose
    Saving energy with just in time instruction delivery. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:178-183 [Conf]
  52. Brad Calder, Daniel Citron, Yale N. Patt, J. Smith
    The future of simulation: A field of dreams. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2004, pp:169- [Conf]
  53. Timothy H. Heil, James E. Smith
    Concurrent Garbage Collection UsingHardware-Assisted Profiling. [Citation Graph (0, 0)][DBLP]
    ISMM, 2000, pp:80-93 [Conf]
  54. Gregory J. Thompson, Zenovy S. Wowczuk, James E. Smith, Wade W. Huebsch, Victor H. Mucino
    Numerical Modeling of School Bus Crash Scenarios. [Citation Graph (0, 0)][DBLP]
    Modelling, Identification and Control, 2003, pp:378-384 [Conf]
  55. Ramon Canal, Antonio González, James E. Smith
    Very low power pipelines using significance compression. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:181-190 [Conf]
  56. Ashutosh S. Dhodapkar, James E. Smith
    Comparing Program Phase Detection Techniques. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:217-227 [Conf]
  57. Roger Espasa, Mateo Valero, James E. Smith
    Out-of-Order Vector Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:160-170 [Conf]
  58. Erik Jacobsen, Eric Rotenberg, James E. Smith
    Assigning Confidence to Conditional Branch Predictions. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:142-152 [Conf]
  59. Quinn Jacobson, Eric Rotenberg, James E. Smith
    Path-Based Next Trace Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:14-23 [Conf]
  60. Timothy H. Heil, James E. Smith
    Relational profiling: enabling thread-level parallelism in virtual machines. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:281-290 [Conf]
  61. Timothy H. Heil, Zak Smith, James E. Smith
    Improving Branch Predictors by Correlating on Data Values. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:28-37 [Conf]
  62. Ho-Seop Kim, James E. Smith
    Hardware Support for Control Transfers in Code Caches. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:253-264 [Conf]
  63. Subbarao Palacharla, James E. Smith
    Decoupling integer execution in superscalar processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:285-290 [Conf]
  64. Eric Rotenberg, Steve Bennett, James E. Smith
    Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:24-35 [Conf]
  65. Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith
    Trace Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:138-148 [Conf]
  66. Eric Rotenberg, James E. Smith
    Control Independence in Trace Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:4-15 [Conf]
  67. Yiannakis Sazeides, James E. Smith
    The Predictability of Data Values. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:248-258 [Conf]
  68. Yiannakis Sazeides, Stamatis Vassiliadis, James E. Smith
    The Performance Potential of Data Dependence Speculation & Collapsing. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:238-247 [Conf]
  69. Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, James E. Smith
    Fair Queuing Memory Systems. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:208-222 [Conf]
  70. Ajeet Shankar, S. Subramanya Sastry, Rastislav Bodík, James E. Smith
    Runtime specialization with optimistic heap analysis. [Citation Graph (0, 0)][DBLP]
    OOPSLA, 2005, pp:327-343 [Conf]
  71. Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas
    Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. [Citation Graph (0, 0)][DBLP]
    PACS, 2002, pp:1-17 [Conf]
  72. S. Subramanya Sastry, Subbarao Palacharla, James E. Smith
    Exploiting Idle Floating-Point Resources for Integer Execution. [Citation Graph (0, 0)][DBLP]
    PLDI, 1998, pp:118-129 [Conf]
  73. Leonidas I. Kontothanassis, Rabin A. Sugumar, Greg Faanes, James E. Smith, Michael L. Scott
    Cache performance in vector supercomputers. [Citation Graph (0, 0)][DBLP]
    SC, 1994, pp:255-264 [Conf]
  74. Corinna G. Lee, James E. Smith
    A Study of Partitioned Vector Register Files. [Citation Graph (0, 0)][DBLP]
    SC, 1992, pp:94-103 [Conf]
  75. James E. Smith, Wei-Chung Hsu
    Prefetching in Supercomputer Instruction Caches. [Citation Graph (0, 0)][DBLP]
    SC, 1992, pp:588-597 [Conf]
  76. James E. Smith, Wei-Chung Hsu, Christopher C. Hsiung
    Future general purpose supercomputer architectures. [Citation Graph (0, 0)][DBLP]
    SC, 1990, pp:796-804 [Conf]
  77. Jason F. Cantin, Mikko H. Lipasti, James E. Smith
    The complexity of verifying memory coherence. [Citation Graph (0, 0)][DBLP]
    SPAA, 2003, pp:254-255 [Conf]
  78. James E. Smith
    A unified view of virtualization. [Citation Graph (0, 0)][DBLP]
    VEE, 2005, pp:1- [Conf]
  79. James E. Smith
    Characterizing Computer Performance with a Single Number. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1988, v:31, n:10, pp:1202-1206 [Journal]
  80. James E. Smith
    Instruction-Level Distributed Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2001, v:34, n:4, pp:59-65 [Journal]
  81. James E. Smith
    Dynamic Instruction Scheduling and the Astronautics ZS-1. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1989, v:22, n:7, pp:21-35 [Journal]
  82. James E. Smith, Ravi Nair
    The Architecture of Virtual Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:5, pp:32-38 [Journal]
  83. James E. Smith, Sriram Vajapeyam
    Trace Processors: Moving to Fourth-Generation Microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:9, pp:68-74 [Journal]
  84. James E. Smith, Shlomo Weiss
    PowerPC 601 and Alpha 21064: A Tale of Two RISCs. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1994, v:27, n:6, pp:46-58 [Journal]
  85. Joshua J. Yi, Lieven Eeckhout, David J. Lilja, Brad Calder, Lizy Kurian John, James E. Smith
    The Future of Simulation: A Field of Dreams. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2006, v:39, n:11, pp:22-29 [Journal]
  86. Yiannakis Sazeides, James E. Smith
    Limits of Data Value Predictability. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:4, pp:229-256 [Journal]
  87. George Cai, Ashutosh S. Dhodapkar, James E. Smith
    Integrated Performance, Power, and Thermal Modeling. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:6, pp:659-0 [Journal]
  88. Eric Rotenberg, James E. Smith
    Control Independence in Trace Processors. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  89. Howard Jay Siegel, Seth Abraham, William L. Bain, Kenneth E. Batcher, Thomas L. Casavant, Doug DeGroot, Jack B. Dennis, David C. Douglas, Tse-Yun Feng, James R. Goodman, Alan Huang, Harry F. Jordan, J. Robert Jamp, Yale N. Patt, Alan Jay Smith, James E. Smith, Lawrence Snyder, Harold S. Stone, Russ Tuck, Benjamin W. Wah
    Report of the Purdue Workshop on Grand Challenges in Computer Architecture for the Support of High Performance Computing. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1992, v:16, n:3, pp:199-211 [Journal]
  90. Lieven Eeckhout, Sébastien Nussbaum, James E. Smith, Koen De Bosschere
    Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:5, pp:26-38 [Journal]
  91. Jason F. Cantin, James E. Smith, Mikko H. Lipasti, Andreas Moshovos, Babak Falsafi
    Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:70-79 [Journal]
  92. Kyle J. Nesbit, James E. Smith
    Data Cache Prefetching Using a Global History Buffer. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:1, pp:90-97 [Journal]
  93. Craig S. Holt, James E. Smith
    Diagnosis of Systems with Asymmetric Invalidation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:9, pp:679-690 [Journal]
  94. Craig S. Holt, James E. Smith
    Self-Diagnosis in Distributed Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:1, pp:19-32 [Journal]
  95. Wei-Chung Hsu, James E. Smith
    A Performance Study of Instruction Cache Prefetching Methods. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:5, pp:497-508 [Journal]
  96. Eric Rotenberg, Steve Bennett, James E. Smith
    A Trace Cache Microarchitecture and Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:111-120 [Journal]
  97. James E. Smith
    On the Existence of Combinational Logic Circuits Exhibiting Multiple Redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:12, pp:1221-1226 [Journal]
  98. James E. Smith
    Universal System Diagnosis Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:5, pp:374-378 [Journal]
  99. James E. Smith
    On Necessary and Sufficient Conditions for Multiple Fault Undetectability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:10, pp:801-802 [Journal]
  100. James E. Smith
    Detection of Faults in Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:11, pp:845-853 [Journal]
  101. James E. Smith
    Comments on ``Redundancy Testing in Combinational Networks''. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:3, pp:261-262 [Journal]
  102. James E. Smith
    Measures of the Effectiveness of Fault Signature Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:6, pp:510-514 [Journal]
  103. James E. Smith
    On Separable Unordered Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:8, pp:741-743 [Journal]
  104. James E. Smith, James R. Goodman
    Instruction Cache Replacement Policies and Organizations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:3, pp:234-241 [Journal]
  105. James E. Smith, Paklin Lam
    A Theory of Totally Self-Checking System Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:831-844 [Journal]
  106. James E. Smith, Gernot Metze
    Strongly Fault Secure Logic Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:6, pp:491-499 [Journal]
  107. James E. Smith, Andrew R. Pleszkun
    Implementing Precise Interrupts in Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:5, pp:562-573 [Journal]
  108. James E. Smith, Shlomo Weiss, Nicholas Y. Pang
    A Simulation Study of Decoupled Architecture Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:8, pp:692-702 [Journal]
  109. Shlomo Weiss, James E. Smith
    Instruction Issue Logic in Pipelined Supercomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:11, pp:1013-1022 [Journal]
  110. James E. Smith
    Decoupled Access/Execute Computer Architectures [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1984, v:2, n:4, pp:289-308 [Journal]
  111. Shlomo Weiss, James E. Smith
    A study of scalar compilation techniques for pipelined supercomputers. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Math. Softw., 1990, v:16, n:3, pp:223-245 [Journal]
  112. Jason F. Cantin, Mikko H. Lipasti, James E. Smith
    The Complexity of Verifying Memory Coherence and Consistency. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:7, pp:663-671 [Journal]
  113. T. N. Vijaykumar, Sridhar Gopal, James E. Smith, Gurindar S. Sohi
    Speculative Versioning Cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2001, v:12, n:12, pp:1305-1317 [Journal]
  114. Marco Galluzzi, Enrique Vallejo, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero
    Implicit Transactional Memory in Kilo-Instruction Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:339-353 [Conf]
  115. Kyle J. Nesbit, James Laudon, James E. Smith
    Virtual private caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:57-68 [Conf]
  116. Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith
    Configurable isolation: building high availability systems with commodity multi-core processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:470-481 [Conf]
  117. Tejas Karkhanis, James E. Smith
    Automated design of application specific superscalar processors: an analytical approach. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:402-411 [Conf]
  118. Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith
    A Top-Down Approach to Architecting CPI Component Performance Counters. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:84-93 [Journal]

  119. Studying Compiler-Microarchitecture Interactions through Interval Analysis. [Citation Graph (, )][DBLP]


  120. Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis. [Citation Graph (, )][DBLP]


  121. An approach for implementing efficient superscalar CISC processors. [Citation Graph (, )][DBLP]


  122. Power-Efficient DRAM Speculation. [Citation Graph (, )][DBLP]


  123. A Mathematical Model of Robust Military Village Searches for Decision Making Purposes. [Citation Graph (, )][DBLP]


  124. Characterizing the branch misprediction penalty. [Citation Graph (, )][DBLP]


  125. Implementing high availability memory with a duplication cache. [Citation Graph (, )][DBLP]


  126. Isolation in Commodity Multicore Processors. [Citation Graph (, )][DBLP]


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