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Arindam Mukherjee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lars Frank, Arindam Mukherjee
    Distributed Electronic Patient Encounter With High Performance and Availability. [Citation Graph (0, 0)][DBLP]
    CBMS, 2002, pp:373-376 [Conf]
  2. Arindam Mukherjee, Ranganathan Sudhakar, Malgorzata Marek-Sadowska, Stephen I. Long
    Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:466-471 [Conf]
  3. Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
    Latency and Latch Count Minimization in Wave Steered Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:383-388 [Conf]
  4. Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska
    Sizing Power/Ground Meshes for Clocking and Computing Circuit Components. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:176-185 [Conf]
  5. Nobuo Funabiki, Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
    A Global Routing Technique for Wave-Steering Design Methodology. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:430-437 [Conf]
  6. Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
    Interconnect pipelining in a throughput-intensive FPGA architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:153-160 [Conf]
  7. Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska
    A novel high throughput reconfigurable FPGA architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:22-29 [Conf]
  8. Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktish Sankaranarayan
    A practical CAD technique for reducing power/ground noise in DSM circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:96-99 [Conf]
  9. Arindam Mukherjee
    On the Reduction of Simultaneous Switching in SoCs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:262-263 [Conf]
  10. Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee, Amit Singh
    Interconnect complexity-aware FPGA placement using Rent's rule. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:115-121 [Conf]
  11. Arindam Mukherjee, Malgorzata Marek-Sadowska
    Clock and Power Gating with Timing Closure. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:32-39 [Journal]
  12. Daniel Davids, Siddhartha Datta, Arindam Mukherjee, Bharat Joshi, Arun Ravindran
    Multiple fault diagnosis in digital microfluidic biochips. [Citation Graph (0, 0)][DBLP]
    JETC, 2006, v:2, n:4, pp:262-276 [Journal]
  13. Kushal Datta, Arindam Mukherjee, Arun Ravindran
    Automated design flow for diode-based nanofabrics. [Citation Graph (0, 0)][DBLP]
    JETC, 2006, v:2, n:3, pp:219-241 [Journal]
  14. Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska
    PITIA: an FPGA for throughput-intensive applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:354-363 [Journal]
  15. Arindam Mukherjee, Malgorzata Marek-Sadowska
    Wave steering to integrate logic and physical syntheses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:105-120 [Journal]
  16. Srikanth Mohan, Arun Ravindran, David Binkley, Arindam Mukherjee
    Power Optimized Design of CMOS Programmable Gain Amplifiers. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:259-270 [Journal]
  17. Steven D. Tucker, Arun Ravindran, Christopher Wichman, Arindam Mukherjee
    Design Techniques for Micro-Power Algorithmic Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:60-69 [Journal]
  18. Fei Su, William L. Hwang, Arindam Mukherjee, Krishnendu Chakrabarty
    Testing and Diagnosis of Realistic Defects in Digital Microfluidic Biochips. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:2-3, pp:219-233 [Journal]

  19. Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer. [Citation Graph (, )][DBLP]

  20. Fault-tolerant wearable computing system architecture for self-health management. [Citation Graph (, )][DBLP]

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