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Swapna Banerjee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bipul Das, Swapna Banerjee
    Homogeneity Induced Inertial Snake with Application to Medical Image Segmentation. [Citation Graph (0, 0)][DBLP]
    CBMS, 2004, pp:304-309 [Conf]
  2. Abhijeet Jadhav, Swapna Banerjee, P. K. Dutta, R. R. Paul, Mausami Pal, P. Banerjee, K. Chaudhuri, J. Chatterjee
    Quantitative Analysis of Histopathological Features of Precancerous Lesion and Condition Using Image Processing Technique. [Citation Graph (0, 0)][DBLP]
    CBMS, 2006, pp:231-236 [Conf]
  3. Abhishek Mitra, Swapna Banerjee
    A New Interpolation Free Method for X-ray CT Image Reconstruction. [Citation Graph (0, 0)][DBLP]
    CBMS, 2004, pp:54-0 [Conf]
  4. Bipul Das, Swapna Banerjee
    A Wavelet Based Low Complexity Embedded Block Coding Algorithm. [Citation Graph (0, 0)][DBLP]
    DCC, 2002, pp:452- [Conf]
  5. Bipul Das, Swapna Banerjee
    A Novel Ram Architecture For Bit-Plane Based Coding. [Citation Graph (0, 0)][DBLP]
    DCC, 2003, pp:421- [Conf]
  6. Bipul Das, Swapna Banerjee
    A CORDIC based array architecture for complex discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:79-84 [Conf]
  7. Bipul Das, S. K. Mitra, Swapna Banerjee
    Knowledge Base System for Diagnostic Assessment of Doppler Spectogram. [Citation Graph (0, 0)][DBLP]
    MICAI, 2000, pp:405-416 [Conf]
  8. J. Bhattacharyya, P. Mandal, R. Banerjee, Swapna Banerjee
    Real Time Dynamic Receive Apodization for an Ultrasound Imaging System. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:534-537 [Conf]
  9. Sanjoy Kr. Dey, Swapna Banerjee
    An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADC. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:593-598 [Conf]
  10. Bipul Das, Swapna Banerjee
    A Memory Efficient 3-D DWT Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:208-0 [Conf]
  11. Debashis Dutta, Wouter A. Serdijn, Swapna Banerjee, Sriram Gupta
    A New CMOS Current Conveyors Based Translinear Loop for Log-Domain Circuit Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:850-853 [Conf]
  12. Debashis Dutta, Ritesh Ujjwal, Swapna Banerjee
    Design of Low-Voltage Low-Power Continuous-Time Filter for Hearing Aid Application Using CMOS Current Conveyor Based Translinear Loop. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:587-592 [Conf]
  13. Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey
    A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm2 Segmented Current Steering CMOS DAC. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:319-322 [Conf]
  14. Samiran Halder, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Swapna Banerjee
    A 160MSPS 8-Bit Pipeline Based ADC. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:313-318 [Conf]
  15. G. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee
    Analysis of temperature dependence of Si-Ge HBT. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:268-271 [Conf]
  16. G. Hari Rama Krishna, Nirmal B. Chakrabarti, Swapna Banerjee
    Finite Element Analysis of SIGe npn HBT. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:319-322 [Conf]
  17. Manisha Pattanaik, Swapna Banerjee
    A New Approach to Analyze a Sub-micron CMOS Inverter. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:116-121 [Conf]
  18. S. K. Mitra, Swapna Banerjee
    On the Probability Distribution of Round-off Errors Propagated in Tabular Differences. [Citation Graph (0, 0)][DBLP]
    Australian Computer Journal, 1971, v:3, n:2, pp:60-68 [Journal]
  19. Koushik Maharatna, Swapna Banerjee
    A VLSI array architecture for Hough transform. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 2001, v:34, n:7, pp:1503-1512 [Journal]
  20. G. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee
    Finite element analysis of SiGe heterojunction devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:7, pp:803-814 [Journal]
  21. Koushik Maharatna, Swapna Banerjee, Eckhard Grass, Milos Krstic, Alfonso Troya
    Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:11, pp:1463-1474 [Journal]
  22. Koushik Maharatna, A. S. Dhar, Swapna Banerjee
    A VLSI array architecture for realization of DFT, DHT, DCT and DST. [Citation Graph (0, 0)][DBLP]
    Signal Processing, 2001, v:81, n:9, pp:1813-1822 [Journal]
  23. Ayan Banerjee, Anindya Sundar Dhar, Swapna Banerjee
    FPGA realization of a CORDIC based FFT processor for biomedical signal processing. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2001, v:25, n:3, pp:131-142 [Journal]

  24. Multirate scan conversion of ultrasound images using warped distance based adaptive bilinear interpolation. [Citation Graph (, )][DBLP]


  25. Efficient VLSI architecture for bit plane encoder of JPEG 2000. [Citation Graph (, )][DBLP]


  26. An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. [Citation Graph (, )][DBLP]


  27. A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier. [Citation Graph (, )][DBLP]


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