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Publications of Author

1. Daniel Ortega, Eduard Ayguadé, Jean-Loup Baer, Mateo Valero
   Cost-Effective Compiler Directed Memory Prefetching and Bypassing. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2002, pp:189-198 [Conf]
   
2. Daniel Ortega, Ivan Martel, Venkata Krishnan, Eduard Ayguadé, Mateo Valero
   Quantifying the Benefits of SPECint Distant Parallelism in Simultaneous Multi-Threading Architectures. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 1999, pp:117-124 [Conf]
   
3. Daniel Ortega, Salvador Revelo, José Mariano Fernández, Pedro Bañuelos
   Output Voltage Effects in a 2x2 SMC Caused by Time Index Change. [Citation Graph (0, 0)][DBLP]
   CONIELECOMP, 2005, pp:100-105 [Conf]
   
4. Sherif M. Yacoub, John Burns, Paolo Faraboschi, Daniel Ortega, José L. Abad Peiro, Vinay Saxena
   Document digitization lifecycle for complex magazine collection. [Citation Graph (0, 0)][DBLP]
   ACM Symposium on Document Engineering, 2005, pp:197-206 [Conf]
   
5. Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
   Out-of-Order Commit Processors. [Citation Graph (0, 0)][DBLP]
   HPCA, 2004, pp:48-59 [Conf]
   
6. Ivan Martel, Daniel Ortega, Eduard Ayguadé, Mateo Valero
   Increasing effective IPC by exploiting distant parallelism. [Citation Graph (0, 0)][DBLP]
   International Conference on Supercomputing, 1999, pp:348-355 [Conf]
   
7. Daniel Ortega, Eduard Ayguadé, Mateo Valero
   Dynamic memory instruction bypassing. [Citation Graph (0, 0)][DBLP]
   ICS, 2003, pp:316-325 [Conf]
   
8. Daniel Ortega, Mateo Valero, Eduard Ayguadé
   A novel renaming mechanism that boosts software prefetching. [Citation Graph (0, 0)][DBLP]
   ICS, 2001, pp:501-510 [Conf]
   
9. Rubén González, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero
   A Content Aware Integer Register File Organization. [Citation Graph (0, 0)][DBLP]
   ISCA, 2004, pp:314-324 [Conf]
   
10. Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
    Kilo-instruction Processors. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:10-25 [Conf]
    
11. Daniel Ortega, Mateo Valero, Eduard Ayguadé
    Dynamic Memory Instruction Bypassing. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2004, v:32, n:3, pp:199-224 [Journal]
    
12. 
    Topic 13: High-Performance Networks. [Citation Graph (, )][DBLP]
    
    
13. 
    An Adaptive Synchronization Technique for Parallel Simulation of Networked Clusters. [Citation Graph (, )][DBLP]
    
    
14. 
    Combining Simulation and Virtualization through Dynamic Sampling. [Citation Graph (, )][DBLP]
    
    
15. 
    High-speed network modeling for full system simulation. [Citation Graph (, )][DBLP]