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Eduard Ayguadé: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Daniel Ortega, Eduard Ayguadé, Jean-Loup Baer, Mateo Valero
    Cost-Effective Compiler Directed Memory Prefetching and Bypassing. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:189-198 [Conf]
  2. Daniel Ortega, Ivan Martel, Venkata Krishnan, Eduard Ayguadé, Mateo Valero
    Quantifying the Benefits of SPECint Distant Parallelism in Simultaneous Multi-Threading Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:117-124 [Conf]
  3. Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé
    Using Sacks to Organize Registers in VLIW Machines. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1994, pp:628-639 [Conf]
  4. Mateo Valero, Montse Peiron, Eduard Ayguadé
    Memory Access Synchronization in Vector Multiprocessors. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1994, pp:414-425 [Conf]
  5. Jordi Torres, Eduard Ayguadé, Jesús Labarta, José M. Llabería, Mateo Valero
    On Automatic Loop Data-Mapping for Distributed-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    EDMCC, 1991, pp:173-182 [Conf]
  6. Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec
    Topic 08+13: Instruction-Level Parallelism and Computer Architecture. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:385- [Conf]
  7. Eduard Ayguadé, Wolfgang Karl, Koen De Bosschere, Jean-Francois Collard
    Topic 7: Parallel Computer Architecture and Instruction Level Parallelism. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2006, pp:459- [Conf]
  8. Xavier Martorell, Jesús Labarta, Nacho Navarro, Eduard Ayguadé
    A Library Implementation of the Nano-Threads Programming Model. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. II, 1996, pp:644-649 [Conf]
  9. Josep Llosa, Mateo Valero, Eduard Ayguadé
    Non-Consistent Dual Register Files to Reduce Register Pressure. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:22-31 [Conf]
  10. Vicenç Beltran, David Carrera, Jordi Guitart, Jordi Torres, Eduard Ayguadé
    A Hybrid Web Server Architecture for Secure e-Business Web Applications. [Citation Graph (0, 0)][DBLP]
    HPCC, 2005, pp:366-377 [Conf]
  11. David Carrera, Vicenç Beltran, Jordi Torres, Eduard Ayguadé
    A Hybrid Web Server Architecture for e-Commerce Applications. [Citation Graph (0, 0)][DBLP]
    ICPADS (1), 2005, pp:182-188 [Conf]
  12. Eduard Ayguadé, Xavier Martorell, Jesús Labarta, Marc González, Nacho Navarro
    Exploiting Multiple Levels of Parallelism in OpenMP: A Case Study. [Citation Graph (0, 0)][DBLP]
    ICPP, 1999, pp:172-180 [Conf]
  13. Vicenç Beltran, David Carrera, Jordi Torres, Eduard Ayguadé
    Evaluating the Scalability of Java Event-Driven Web Servers. [Citation Graph (0, 0)][DBLP]
    ICPP, 2004, pp:134-142 [Conf]
  14. Jordi Guitart, David Carrera, Vicenç Beltran, Jordi Torres, Eduard Ayguadé
    Session-Based Adaptive Overload Control for Secure Dynamic Web Applications. [Citation Graph (0, 0)][DBLP]
    ICPP, 2005, pp:341-349 [Conf]
  15. Jordi Guitart, Jordi Torres, Eduard Ayguadé, J. Mark Bull
    Performance Analysis Tools for Parallel Java Applications on Shared-memory Systems. [Citation Graph (0, 0)][DBLP]
    ICPP, 2001, pp:357-364 [Conf]
  16. Marc González, Eduard Ayguadé, Xavier Martorell, Jesús Labarta
    Complex Pipelined Executions in OpenMP Parallel Applications. [Citation Graph (0, 0)][DBLP]
    ICPP, 2001, pp:295-304 [Conf]
  17. David López, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP, 1999, pp:22-29 [Conf]
  18. Dimitrios S. Nikolopoulos, Theodore S. Papatheodorou, Constantine D. Polychronopoulos, Jesús Labarta, Eduard Ayguadé
    User-Level Dynamic Page Migration for Multiprogrammed Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:95-104 [Conf]
  19. Eduard Ayguadé, Jordi Torres
    Partitioning the Statement per Iteration Space Using Non-Singular Matrices. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1993, pp:407-415 [Conf]
  20. Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam, Eduard Ayguadé
    An integer linear programming approach for optimizing cache locality. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:500-509 [Conf]
  21. David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
    Resource Widening Versus Replication: Limits and Performance-cost Trade-off. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:441-448 [Conf]
  22. David López, Mateo Valero, Josep Llosa, Eduard Ayguadé
    Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:12-19 [Conf]
  23. Dimitrios S. Nikolopoulos, Eduard Ayguadé, Theodore S. Papatheodorou, Constantine D. Polychronopoulos, Jesús Labarta
    The trade-off between implicit and explicit data distribution in shared-memory programming paradigms. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:23-37 [Conf]
  24. Ivan Martel, Daniel Ortega, Eduard Ayguadé, Mateo Valero
    Increasing effective IPC by exploiting distant parallelism. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:348-355 [Conf]
  25. Xavier Martorell, Eduard Ayguadé, Nacho Navarro, Julita Corbalán, Marc González, Jesús Labarta
    Thread fork/join techniques for multi-level parallelism exploitation in NUMA multiprocessors. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:294-301 [Conf]
  26. Dimitrios S. Nikolopoulos, Theodore S. Papatheodorou, Constantine D. Polychronopoulos, Jesús Labarta, Eduard Ayguadé
    A case for use-level dynamic page migration. [Citation Graph (0, 0)][DBLP]
    ICS, 2000, pp:119-130 [Conf]
  27. Daniel Ortega, Eduard Ayguadé, Mateo Valero
    Dynamic memory instruction bypassing. [Citation Graph (0, 0)][DBLP]
    ICS, 2003, pp:316-325 [Conf]
  28. Daniel Ortega, Mateo Valero, Eduard Ayguadé
    A novel renaming mechanism that boosts software prefetching. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:501-510 [Conf]
  29. Montse Peiron, Mateo Valero, Eduard Ayguadé
    Synchronized access to streams in SIMD vector multiprocessors. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1994, pp:23-32 [Conf]
  30. Mateo Valero, Tomás Lang, Eduard Ayguadé
    Conflict-free access of vectors with power-of-two strides. [Citation Graph (0, 0)][DBLP]
    ICS, 1992, pp:149-156 [Conf]
  31. Eduard Ayguadé, Marc González, Xavier Martorell, Gabriele Jost
    Employing Nested OpenMP for the Parallelization of Multi-Zone Computational Fluid Dynamics Applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  32. J. J. Costa, Toni Cortes, Xavier Martorell, Eduard Ayguadé, Jesús Labarta
    Running OpenMP Applications Efficiently on an Everything-Shared SDSM. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  33. Jordi Guitart, Vicenç Beltran, David Carrera, Jordi Torres, Eduard Ayguadé
    Characterizing Secure Dynamic Web Applications Scalability. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  34. Jordi Guitart, Xavier Martorell, Jordi Torres, Eduard Ayguadé
    Application/Kernel Cooperation Towards the Efficient Execution of Shared-Memory Parallel Java Codes. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:38- [Conf]
  35. Marc González, Albert Serra, Xavier Martorell, José Oliver, Eduard Ayguadé, Jesús Labarta, Nacho Navarro
    Applying Interposition Techniques for Performance Analysis of OpenMP Parallel Applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:235-240 [Conf]
  36. Xavier Martorell, Jesús Labarta, Nacho Navarro, Eduard Ayguadé
    Analysis of Several Scheduling Algorithms under the Nano-Thread Programming Model. [Citation Graph (0, 0)][DBLP]
    IPPS, 1997, pp:281-287 [Conf]
  37. David Ródenas, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, George Almási, Calin Cascaval, José G. Castaños, José E. Moreira
    Optimizing NANOS OpenMP for the IBM Cyclops Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  38. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Hierarchical Clustered Register File Organization for VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:77- [Conf]
  39. Xavier Martorell, Marc González, Alejandro Duran, Jairo Balart, Roger Ferrer, Eduard Ayguadé, Jesús Labarta
    Techniques supporting threadprivate in OpenMP. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  40. Montse Peiron, Mateo Valero, Eduard Ayguadé, Tomás Lang
    Vector Multiprocessors with Arbitrated Memory Access. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:243-252 [Conf]
  41. Mateo Valero, Tomás Lang, José M. Llabería, Montse Peiron, Eduard Ayguadé, Juan J. Navarro
    Increasing the Number of Strides for Conflict-Free Vector Access. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:372-381 [Conf]
  42. Marc González, Eduard Ayguadé, Xavier Martorell, Jesús Labarta, Phu V. Luong
    Dual-Level Parallelism Exploitation with OpenMP in Coastal Ocean Circulation Modeling. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:469-478 [Conf]
  43. Dimitrios S. Nikolopoulos, Theodore S. Papatheodorou, Constantine D. Polychronopoulos, Jesús Labarta, Eduard Ayguadé
    Leveraging Transparent Data Distribution in OpenMP via User-Level Dynamic Page Migration. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2000, pp:415-427 [Conf]
  44. Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
    Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:113-126 [Conf]
  45. David Carrera, Jordi Guitart, Jordi Torres, Eduard Ayguadé, Jesús Labarta
    Complete instrumentation requirements for performance analysis of Web based technologies. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2003, pp:166-175 [Conf]
  46. José Oliver, Eduard Ayguadé, Nacho Navarro
    Towards an efficient exploitation of loop-level parallelism in Java. [Citation Graph (0, 0)][DBLP]
    Java Grande, 2000, pp:9-15 [Conf]
  47. Eduard Ayguadé, Jordi Garcia, Mercè Gironés, M. Luz Grande, Jesús Labarta
    Data Redistribution in an Automatic Data Distribution Tool. [Citation Graph (0, 0)][DBLP]
    LCPC, 1995, pp:407-421 [Conf]
  48. Eduard Ayguadé, Jordi Garcia, M. Luz Grande, Jesús Labarta
    Data Distribution and Loop Parallelization for Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    LCPC, 1996, pp:41-55 [Conf]
  49. Eduard Ayguadé, Jordi Garcia, Mercè Gironés, Jesús Labarta, Jordi Torres, Mateo Valero
    Detecting and Using Affinity in an Automatic Data Distribution Tool. [Citation Graph (0, 0)][DBLP]
    LCPC, 1994, pp:61-75 [Conf]
  50. Eduard Ayguadé, Xavier Martorell, Jesús Labarta, Marc González, Nacho Navarro
    Exploiting Parallelism Through Directives on the Nano-Threads Programming Model. [Citation Graph (0, 0)][DBLP]
    LCPC, 1997, pp:307-321 [Conf]
  51. Marc González, José Oliver, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Nacho Navarro
    OpenMP Extensions for Thread Groups and Their Run-Time Support. [Citation Graph (0, 0)][DBLP]
    LCPC, 2000, pp:324-338 [Conf]
  52. Jesús Labarta, Eduard Ayguadé, Jordi Torres, Mateo Valero, José M. Llabería
    Balanced Loop Partitioning Using GTS. [Citation Graph (0, 0)][DBLP]
    LCPC, 1991, pp:298-312 [Conf]
  53. Jordi Torres, Eduard Ayguadé, Jesús Labarta, Mateo Valero
    Align and Distribute-based Linear Loop Transformations. [Citation Graph (0, 0)][DBLP]
    LCPC, 1993, pp:321-339 [Conf]
  54. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    MIRS: Modulo Scheduling with Integrated Register Spilling. [Citation Graph (0, 0)][DBLP]
    LCPC, 2001, pp:239-253 [Conf]
  55. Dimitrios S. Nikolopoulos, Theodore S. Papatheodorou, Constantine D. Polychronopoulos, Jesús Labarta, Eduard Ayguadé
    UPMLIB: A Runtime System for Tuning the Memory Performance of OpenMP Programs on Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    LCR, 2000, pp:85-99 [Conf]
  56. Josep Llosa, Mateo Valero, Eduard Ayguadé
    Heuristics for Register-Constrained Software Pipelining. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:250-261 [Conf]
  57. Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
    Hypernode reduction modulo scheduling. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:350-360 [Conf]
  58. David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
    Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:237-246 [Conf]
  59. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Two-level hierarchical register file organization for VLIW processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:137-146 [Conf]
  60. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Modulo scheduling with integrated register spilling for clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:160-169 [Conf]
  61. Jesús Labarta, Eduard Ayguadé
    GTS: Extracting Full Parallelism Out of DO Loops. [Citation Graph (0, 0)][DBLP]
    PARLE (2), 1989, pp:43-54 [Conf]
  62. David Carrera, David Garcia, Jordi Torres, Eduard Ayguadé, Jesús Labarta
    WAS Control Center: An Autonomic Performance-Triggered Tracing Environment for WebSphere. [Citation Graph (0, 0)][DBLP]
    PDP, 2005, pp:26-32 [Conf]
  63. Jordi Guitart, David Carrera, Jordi Torres, Eduard Ayguadé, Jesús Labarta
    Tuning Dynamic Web Applications using Fine-Grain Analysis. [Citation Graph (0, 0)][DBLP]
    PDP, 2005, pp:84-91 [Conf]
  64. Roger Espasa, Mateo Valero, David A. Padua, Marta Jiménez, Eduard Ayguadé
    Quantitative analysis of vector code. [Citation Graph (0, 0)][DBLP]
    PDP, 1995, pp:452-463 [Conf]
  65. Jordi Torres, Eduard Ayguadé, Jesús Labarta, Mateo Valero
    Loop Parallelization: Revisiting Framework of Unimodular Transformations. [Citation Graph (0, 0)][DBLP]
    PDP, 1996, pp:420-428 [Conf]
  66. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Improved spill code generation for software pipelined loops. [Citation Graph (0, 0)][DBLP]
    PLDI, 2000, pp:134-144 [Conf]
  67. Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
    with Wide Functional Units. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:88-97 [Conf]
  68. Jordi Garcia, Eduard Ayguadé, Jesús Labarta
    A Novel Approach Towards Automatic Data Distribution. [Citation Graph (0, 0)][DBLP]
    SC, 1995, pp:- [Conf]
  69. Dimitrios S. Nikolopoulos, Constantine D. Polychronopoulos, Eduard Ayguadé
    Scaling irregular parallel codes with minimal programming effort. [Citation Graph (0, 0)][DBLP]
    SC, 2001, pp:16- [Conf]
  70. Dimitrios S. Nikolopoulos, Theodore S. Papatheodorou, Constantine D. Polychronopoulos, Jesús Labarta, Eduard Ayguadé
    Is Data Distribution Necessary in OpenMP? [Citation Graph (0, 0)][DBLP]
    SC, 2000, pp:- [Conf]
  71. George S. Almasi, Eduard Ayguadé, Calin Cascaval, José G. Castaños, Jesús Labarta, Francisco Martínez, Xavier Martorell, José E. Moreira
    Evaluation of OpenMP for the Cyclops Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
    WOMPAT, 2003, pp:69-83 [Conf]
  72. Eduard Ayguadé, Bob Blainey, Alejandro Duran, Jesús Labarta, Francisco Martínez, Xavier Martorell, Raúl Silvera
    Is the Schedule Clause Really Necessary in OpenMP? [Citation Graph (0, 0)][DBLP]
    WOMPAT, 2003, pp:147-159 [Conf]
  73. Marc González, Eduard Ayguadé, Xavier Martorell, Jesús Labarta
    Defining and Supporting Pipelined Executions in OpenMP. [Citation Graph (0, 0)][DBLP]
    WOMPAT, 2001, pp:155-169 [Conf]
  74. Dimitrios S. Nikolopoulos, Eduard Ayguadé
    A Study of Implicit Data Distribution Methods for OpenMP Using the SPEC Benchmarks. [Citation Graph (0, 0)][DBLP]
    WOMPAT, 2001, pp:115-129 [Conf]
  75. Marc González, Eduard Ayguadé, Xavier Martorell, Jesús Labarta, Nacho Navarro, José Oliver
    NanosCompiler: supporting flexible multilevel parallelism exploitation in OpenMP. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 2000, v:12, n:12, pp:1205-1218 [Journal]
  76. José Oliver, Jordi Guitart, Eduard Ayguadé, Nacho Navarro, Jordi Torres
    Strategies for the efficient exploitation of loop-level parallelism in Java. [Citation Graph (0, 0)][DBLP]
    Concurrency and Computation: Practice and Experience, 2001, v:13, n:8-9, pp:663-680 [Journal]
  77. Josep Llosa, Eduard Ayguadé, Mateo Valero
    Quantitative Evaluation of Register Pressure on Software Pipelined Loops. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:2, pp:121-142 [Journal]
  78. Dimitrios S. Nikolopoulos, Eduard Ayguadé, Constantine D. Polychronopoulos
    Runtime vs. Manual Data Distribution for Architecture-Agnostic Shared-Memory Programming Models. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2002, v:30, n:4, pp:225-255 [Journal]
  79. Daniel Ortega, Mateo Valero, Eduard Ayguadé
    Dynamic Memory Instruction Bypassing. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2004, v:32, n:3, pp:199-224 [Journal]
  80. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2004, v:32, n:6, pp:447-474 [Journal]
  81. Dimitrios S. Nikolopoulos, Constantine D. Polychronopoulos, Theodore S. Papatheodorou, Jesús Labarta, Eduard Ayguadé
    Scheduler-Activated Dynamic Page Migration for Multiprogrammed DSM Multiprocessors. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2002, v:62, n:6, pp:1069-1103 [Journal]
  82. J. J. Costa, Toni Cortes, Xavier Martorell, Eduard Ayguadé, Jesús Labarta
    Running OpenMP applications efficiently on an everything-shared SDSM. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2006, v:66, n:5, pp:647-658 [Journal]
  83. Eduard Ayguadé, Marc González, Xavier Martorell, Gabriele Jost
    Employing nested OpenMP for the parallelization of multi-zone computational fluid dynamics applications. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2006, v:66, n:5, pp:686-697 [Journal]
  84. Eduard Ayguadé, Jordi Garcia, Ulrich Kremer
    Tools and Techniques for Automatic Data Layout: A Case Study. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1998, v:24, n:3-4, pp:557-578 [Journal]
  85. Mateo Valero, Eduard Ayguadé, Montse Peiron
    Network Synchronization and Out-of-Order Access to Vectors. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1994, v:4, n:, pp:405-415 [Journal]
  86. Mateo Valero, Tomás Lang, José María Llabería, Montse Peiron, Juan J. Navarro, Eduard Ayguadé
    Conflict-Free Strides for Vectors in Matched Memories. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1991, v:1, n:, pp:95-102 [Journal]
  87. Dimitrios S. Nikolopoulos, Ernest Artiaga, Eduard Ayguadé, Jesús Labarta
    Exploiting memory affinity in OpenMP through schedule reuse. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2001, v:29, n:5, pp:49-55 [Journal]
  88. Eduard Ayguadé, B. Chapman
    Introduction. [Citation Graph (0, 0)][DBLP]
    Scientific Programming, 2003, v:11, n:2, pp:79-80 [Journal]
  89. Dimitrios S. Nikolopoulos, Ernest Artiaga, Eduard Ayguadé, Jesús Labarta
    Scaling non-regular shared-memory codes by reusing custom loop schedules. [Citation Graph (0, 0)][DBLP]
    Scientific Programming, 2003, v:11, n:2, pp:143-158 [Journal]
  90. Jesús Labarta, Eduard Ayguadé, José Oliver, D. S. Henty
    New OpenMP directives for irregular data access loops. [Citation Graph (0, 0)][DBLP]
    Scientific Programming, 2001, v:9, n:2-3, pp:175-183 [Journal]
  91. Haoqiang Jin, Gabriele Jost, Jerry Yan, Eduard Ayguadé, Marc González, Xavier Martorell
    Automatic multilevel parallelization using OpenMP. [Citation Graph (0, 0)][DBLP]
    Scientific Programming, 2003, v:11, n:2, pp:177-190 [Journal]
  92. Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt
    Lifetime-Sensitive Modulo Scheduling in a Production Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:3, pp:234-249 [Journal]
  93. Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
    Modulo Scheduling with Reduced Register Pressure. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:6, pp:625-638 [Journal]
  94. David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
    Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:10, pp:1033-1051 [Journal]
  95. Mateo Valero, Tomás Lang, Montse Peiron, Eduard Ayguadé
    Conflict-Free Access for Streams in Multimodule Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:5, pp:634-646 [Journal]
  96. Jordi Garcia, Eduard Ayguadé, Jesús Labarta
    A Framework for Integrating Data Alignment, Distribution, and Redistribution in Distributed Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2001, v:12, n:4, pp:416-431 [Journal]
  97. Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam, Eduard Ayguadé
    Static and Dynamic Locality Optimizations Using Integer Linear Programming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2001, v:12, n:9, pp:922-941 [Journal]
  98. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Register Constrained Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:5, pp:417-430 [Journal]
  99. Jairo Balart, Marc González, Xavier Martorell, Eduard Ayguadé, Jesús Labarta
    Runtime Address Space Computation for SDSM Systems. [Citation Graph (0, 0)][DBLP]
    LCPC, 2006, pp:330-344 [Conf]
  100. Paul Carpenter, David Ródenas, Xavier Martorell, Alex Ramírez, Eduard Ayguadé
    A Streaming Machine Description and Programming Model. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:107-116 [Conf]
  101. Jordi Guitart, David Carrera, Vicenç Beltran, Jordi Torres, Eduard Ayguadé
    Designing an overload control strategy for secure e-commerce applications. [Citation Graph (0, 0)][DBLP]
    Computer Networks, 2007, v:51, n:15, pp:4492-4510 [Journal]
  102. Eduard Ayguadé, Matthias S. Müller
    Special Issue on OpenMP - Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2007, v:35, n:4, pp:331-333 [Journal]
  103. Alejandro Duran, Roger Ferrer, Juan José Costa, Marc González, Xavier Martorell, Eduard Ayguadé, Jesús Labarta
    A Proposal for Error Handling in OpenMP. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2007, v:35, n:4, pp:393-416 [Journal]
  104. Eduard Ayguadé, Matthias S. Müller
    Introduction. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2007, v:35, n:5, pp:437-439 [Journal]
  105. Tim Harris, Adrián Cristal, Osman S. Unsal, Eduard Ayguadé, Fabrizio Gagliardi, Burton Smith, Mateo Valero
    Transactional Memory: An Overview. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:3, pp:8-29 [Journal]

  106. Hybrid access-specific software cache techniques for the cell BE architecture. [Citation Graph (, )][DBLP]


  107. Support for OpenMP tasks in Nanos v4. [Citation Graph (, )][DBLP]


  108. OpenMP tasks in IBM XL compilers. [Citation Graph (, )][DBLP]


  109. Mapping stream programs onto heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]


  110. Introduction. [Citation Graph (, )][DBLP]


  111. An Extension of the StarSs Programming Model for Platforms with Multiple GPUs. [Citation Graph (, )][DBLP]


  112. Starsscheck: A Tool to Find Errors in Task-Based Parallel Programs. [Citation Graph (, )][DBLP]


  113. CellMT: A cooperative multithreading library for the Cell/B.E. [Citation Graph (, )][DBLP]


  114. Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors. [Citation Graph (, )][DBLP]


  115. Analysis of Task Offloading for Accelerators. [Citation Graph (, )][DBLP]


  116. A CellBE-based HPC Application for the Analysis of Vulnerabilities in Cryptographic Hash Functions. [Citation Graph (, )][DBLP]


  117. Managing SLAs of heterogeneous workloads using dynamic application placement. [Citation Graph (, )][DBLP]


  118. Tailoring Resources: The Energy Efficient Consolidation Strategy Goes Beyond Virtualization. [Citation Graph (, )][DBLP]


  119. Improving Web Server Performance Through Main Memory Compression. [Citation Graph (, )][DBLP]


  120. Speeding Up Distributed MapReduce Applications Using Hardware Accelerators. [Citation Graph (, )][DBLP]


  121. Barcelona OpenMP Tasks Suite: A Set of Benchmarks Targeting the Exploitation of Task Parallelism in OpenMP. [Citation Graph (, )][DBLP]


  122. QuakeTM: parallelizing a complex sequential application using transactional memory. [Citation Graph (, )][DBLP]


  123. Overlapping communication and computation by using a hybrid MPI/SMPSs approach. [Citation Graph (, )][DBLP]


  124. Decomposable and responsive power models for multicore processors using performance counters. [Citation Graph (, )][DBLP]


  125. Understanding tuning complexity in multithreaded and hybrid web servers. [Citation Graph (, )][DBLP]


  126. An Experimental Evaluation of the New OpenMP Tasking Model. [Citation Graph (, )][DBLP]


  127. A Novel Asynchronous Software Cache Implementation for the Cell-BE Processor. [Citation Graph (, )][DBLP]


  128. Adaptive and Speculative Memory Consistency Support for Multi-core Architectures with On-Chip Local Memories. [Citation Graph (, )][DBLP]


  129. Automatic Pre-Fetch and Modulo Scheduling Transformations for the Cell BE Architecture. [Citation Graph (, )][DBLP]


  130. Unrolling Loops Containing Task Parallelism. [Citation Graph (, )][DBLP]


  131. Enabling Resource Sharing between Transactional and Batch Workloads Using Dynamic Application Placement. [Citation Graph (, )][DBLP]


  132. Batch Job Profiling and Adaptive Profile Enforcement for Virtualized Environments. [Citation Graph (, )][DBLP]


  133. Impact of the Memory Hierarchy on Shared Memory Architectures in Multicore Programming Models. [Citation Graph (, )][DBLP]


  134. Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. [Citation Graph (, )][DBLP]


  135. Atomic quake: using transactional memory in an interactive multiplayer game server. [Citation Graph (, )][DBLP]


  136. Effective communication and computation overlap with hybrid MPI/SMPSs. [Citation Graph (, )][DBLP]


  137. The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors. [Citation Graph (, )][DBLP]


  138. OpenMP extensions for FPGA accelerators. [Citation Graph (, )][DBLP]


  139. An adaptive cut-off for task parallelism. [Citation Graph (, )][DBLP]


  140. Transactional Memory and OpenMP. [Citation Graph (, )][DBLP]


  141. A Proposal for Task Parallelism in OpenMP. [Citation Graph (, )][DBLP]


  142. Evaluation of OpenMP Task Scheduling Strategies. [Citation Graph (, )][DBLP]


  143. Extending the OpenMP Tasking Model to Allow Dependent Tasks. [Citation Graph (, )][DBLP]


  144. A Proposal to Extend the OpenMP Tasking Model for Heterogeneous Architectures. [Citation Graph (, )][DBLP]


  145. An Extension to Improve OpenMP Tasking Control. [Citation Graph (, )][DBLP]


  146. A Proposal for User-Defined Reductions in OpenMP. [Citation Graph (, )][DBLP]


  147. Utility-based placement of dynamic Web applications with fairness goals. [Citation Graph (, )][DBLP]


  148. Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors. [Citation Graph (, )][DBLP]


  149. Dynamic CPU provisioning for self-managed secure web applications in SMP hosting platforms. [Citation Graph (, )][DBLP]


  150. A survey on performance management for internet applications. [Citation Graph (, )][DBLP]


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