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Publications of Author

1. Emre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte
   A Fast Interrupt Handling Scheme for VLIW Processors. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 1998, pp:136-141 [Conf]
   
2. Sanjeev Banerjia, William A. Havanki, Thomas M. Conte
   Treegion Scheduling for Highly Parallel Processors. [Citation Graph (0, 0)][DBLP]
   Euro-Par, 1997, pp:1074-1078 [Conf]
   
3. William A. Havanki, Sanjeev Banerjia, Thomas M. Conte
   Treegion Scheduling for Wide Issue Processors. [Citation Graph (0, 0)][DBLP]
   HPCA, 1998, pp:266-276 [Conf]
   
4. Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye
   Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. [Citation Graph (0, 0)][DBLP]
   MICRO, 1996, pp:201-211 [Conf]
   
5. Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia
   A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures. [Citation Graph (0, 0)][DBLP]
   MICRO, 1996, pp:4-13 [Conf]
   
6. Emre Özer, Sanjeev Banerjia, Thomas M. Conte
   Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. [Citation Graph (0, 0)][DBLP]
   MICRO, 1998, pp:308-315 [Conf]
   
7. Vasanth Bala, Evelyn Duesterwald, Sanjeev Banerjia
   Dynamo: a transparent dynamic optimization system. [Citation Graph (0, 0)][DBLP]
   PLDI, 2000, pp:1-12 [Conf]
   
8. Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte
   MPS: Miss-Path Scheduling for Multiple-Issue Processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1998, v:47, n:12, pp:1382-1397 [Journal]