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Sarita V. Adve: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Parthasarathy Ranganathan, Kourosh Gharachorloo, Sarita V. Adve, Luiz André Barroso
    Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors. [Citation Graph (1, 0)][DBLP]
    ASPLOS, 1998, pp:307-318 [Conf]
  2. Sarita V. Adve, Mark D. Hill
    Weak Ordering - A New Definition. [Citation Graph (1, 0)][DBLP]
    ISCA, 1990, pp:2-14 [Conf]
  3. Sarita V. Adve, Kourosh Gharachorloo
    Shared Memory Consistency Models: A Tutorial. [Citation Graph (1, 0)][DBLP]
    IEEE Computer, 1996, v:29, n:12, pp:66-76 [Journal]
  4. Vijay S. Pai, Sarita V. Adve
    Comparing and Combining Read Miss Clustering and Software Prefetching. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:292-0 [Conf]
  5. Xiaodong Li, Zhenmin Li, Francis M. David, Pin Zhou, Yuanyuan Zhou, Sarita V. Adve, Sanjeev Kumar
    Performance directed energy management for main memory and disks. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:271-283 [Conf]
  6. Ruchira Sasanka, Christopher J. Hughes, Sarita V. Adve
    Joint local and global hardware adaptations for energy. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:144-155 [Conf]
  7. Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve, Tracy Harton
    An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1996, pp:12-23 [Conf]
  8. Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers
    SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:496-505 [Conf]
  9. Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
    The Impact of Technology Scaling on Lifetime Reliability. [Citation Graph (0, 0)][DBLP]
    DSN, 2004, pp:177-0 [Conf]
  10. Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
    Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:23-32 [Conf]
  11. Hazim Abdel-Shafi, Jonathan Hall, Sarita V. Adve, Vikram S. Adve
    An Evaluation of Fine-Grain Producer-Initiated Communication in Cache-Coherent Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:204-0 [Conf]
  12. Sarita V. Adve, Alan L. Cox, Sandhya Dwarkadas, Ramakrishnan Rajamony, Willy Zwaenepoel
    A Comparison of Entry Consistency and Lazy Release Consistency Implementations. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:26-37 [Conf]
  13. Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve
    The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:72-83 [Conf]
  14. Daniel Grobe Sachs, Sarita V. Adve, Douglas L. Jones
    Cross-layer adaptive video coding to reduce energy on general-purpose processors. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2003, pp:109-112 [Conf]
  15. Sarita V. Adve, Mark D. Hill
    Implementing Sequential Consistency in Cache-Based Systems. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:47-50 [Conf]
  16. Ruchira Sasanka, Sarita V. Adve, Yen-Kuang Chen, Eric Debes
    The energy efficiency of CMP vs. SMT for multimedia workloads. [Citation Graph (0, 0)][DBLP]
    ICS, 2004, pp:196-206 [Conf]
  17. Jayanth Srinivasan, Sarita V. Adve
    Predictive dynamic thermal management for multimedia applications. [Citation Graph (0, 0)][DBLP]
    ICS, 2003, pp:109-120 [Conf]
  18. Gengbin Zheng, Terry Wilmarth, Orion Sky Lawlor, Laxmikant V. Kalé, Sarita V. Adve, David A. Padua, Philippe Guebelle
    Performance Modeling and Programming Environments for Petaflops Computers and the Blue Gene Machine. [Citation Graph (0, 0)][DBLP]
    IPDPS Next Generation Software Program - NSFNGS - PI Workshop, 2004, pp:- [Conf]
  19. Sarita V. Adve, Vikram S. Adve, Mark D. Hill, Mary K. Vernon
    Comparison of Hardware and Software Cache Coherence Schemes. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:298-308 [Conf]
  20. Sarita V. Adve, Mark D. Hill
    Retrospective: Weak Ordering - A New Definition. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:63-66 [Conf]
  21. Sarita V. Adve, Mark D. Hill
    Weak Ordering - A New Definition. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:363-375 [Conf]
  22. Sarita V. Adve, Mark D. Hill, Barton P. Miller, Robert H. B. Netzer
    Detecting Data Races on Weak Memory Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:234-243 [Conf]
  23. Christopher J. Hughes, Sarita V. Adve
    A Formal Approach to Frequent Energy Adaptations for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:138-149 [Conf]
  24. Christopher J. Hughes, Praful Kaul, Sarita V. Adve, Rohit Jain, Chanik Park, Jayanth Srinivasan
    Variability in the execution of multimedia applications and implications for architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:254-265 [Conf]
  25. Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi
    Reconfigurable caches and their application to media processing. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:214-224 [Conf]
  26. Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi
    Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:124-135 [Conf]
  27. Parthasarathy Ranganathan, Vijay S. Pai, Hazim Abdel-Shafi, Sarita V. Adve
    The Interaction of Software Prefetching with ILP Processors in Shared-Memory Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:144-156 [Conf]
  28. Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, David A. Wood
    Analytic Evaluation of Shared-memory Systems with ILP Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:380-391 [Conf]
  29. Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
    The Case for Lifetime Reliability-Aware Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:276-287 [Conf]
  30. Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
    Exploiting Structural Duplication for Lifetime Reliability Enhancement. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:520-531 [Conf]
  31. Christopher J. Hughes, Jayanth Srinivasan, Sarita V. Adve
    Saving energy with architectural and frequency adaptations for multimedia applications. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:250-261 [Conf]
  32. Vijay S. Pai, Sarita V. Adve
    Code Transformations to Improve Memory Parallelism. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:147-0 [Conf]
  33. Jeremy Manson, William Pugh, Sarita V. Adve
    The Java memory model. [Citation Graph (0, 0)][DBLP]
    POPL, 2005, pp:378-391 [Conf]
  34. Rohit Jain, Christopher J. Hughes, Sarita V. Adve
    Soft Real- Time Scheduling on Simultaneous Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 2002, pp:134-0 [Conf]
  35. Parthasarathy Ranganathan, Vijay S. Pai, Sarita V. Adve
    Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap Between Memory Consistency Models. [Citation Graph (0, 0)][DBLP]
    SPAA, 1997, pp:199-210 [Conf]
  36. Sarita V. Adve, Doug Burger, Rudolf Eigenmann, Alasdair Rawsthorne, Michael D. Smith, Catherine H. Gebotys, Mahmut T. Kandemir, David J. Lilja, Alok N. Choudhary, Jesse Zhixi Fang, Pen-Chung Yew
    Changing Interaction of Compiler and Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:51-58 [Journal]
  37. Christopher J. Hughes, Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve
    RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:2, pp:40-49 [Journal]
  38. Shubhendu S. Mukherjee, Sarita V. Adve, Todd M. Austin, Joel S. Emer, Peter S. Magnusson
    Performance Simulation Tools. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:2, pp:38-39 [Journal]
  39. Vijay S. Pai, Sarita V. Adve
    Code Transformations to Improve Memory Parallelism. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  40. Kourosh Gharachorloo, Sarita V. Adve, Anoop Gupta, John L. Hennessy, Mark D. Hill
    Programming for Different Memory Consistency Models. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1992, v:15, n:4, pp:399-407 [Journal]
  41. Christopher J. Hughes, Sarita V. Adve
    Memory-side prefetching for linked data structures for processor-in-memory systems. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2005, v:65, n:4, pp:448-463 [Journal]
  42. Sarita V. Adve, Pia Sanda
    Guest Editors' Introduction: Reliability-Aware Microarchitecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:6, pp:8-9 [Journal]
  43. Xiaodong Li, Zhenmin Li, Pin Zhou, Yuanyuan Zhou, Sarita V. Adve, Sanjeev Kumar
    Performance-Directed Energy Management for Storage Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:38-49 [Journal]
  44. Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
    Lifetime Reliability: Toward an Architectural Solution. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:3, pp:70-80 [Journal]
  45. Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, Sarita V. Adve
    The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:218-226 [Journal]
  46. Wanghong Yuan, Klara Nahrstedt, Sarita V. Adve, Douglas L. Jones, Robin Kravets
    GRACE-1: Cross-Layer Adaptation for Multimedia Quality and Battery Energy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Mob. Comput., 2006, v:5, n:7, pp:799-815 [Journal]
  47. Xiaodong Li, Zhenmin Li, Yuanyuan Zhou, Sarita V. Adve
    Performance directed energy management for main memory and disks. [Citation Graph (0, 0)][DBLP]
    TOS, 2005, v:1, n:3, pp:346-380 [Journal]
  48. Sarita V. Adve, Mark D. Hill
    A Unified Formalization of Four Shared-Memory Models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:6, pp:613-624 [Journal]
  49. Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers
    Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:266-275 [Conf]
  50. Soyeon Park, Weihang Jiang, Yuanyuan Zhou, Sarita V. Adve
    Managing energy-performance tradeoffs for multithreaded applications on multiprocessor architectures. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2007, pp:169-180 [Conf]
  51. Ruchira Sasanka, Man-Lap Li, Sarita V. Adve, Yen-Kuang Chen, Eric Debes
    ALP: Efficient support for all levels of parallelism for complex media applications. [Citation Graph (0, 0)][DBLP]
    TACO, 2007, v:4, n:1, pp:- [Journal]
  52. Xiaodong Li, Ritu Gupta, Sarita V. Adve, Yuanyuan Zhou
    Cross-component energy management: Joint adaptation of processor and memory. [Citation Graph (0, 0)][DBLP]
    TACO, 2007, v:4, n:3, pp:- [Journal]

  53. Understanding the propagation of hard errors to software and implications for resilient system design. [Citation Graph (, )][DBLP]


  54. Using likely program invariants to detect hardware errors. [Citation Graph (, )][DBLP]


  55. Trace-based microarchitecture-level diagnosis of permanent hardware faults. [Citation Graph (, )][DBLP]


  56. Accurate microarchitecture-level fault modeling for studying hardware faults. [Citation Graph (, )][DBLP]


  57. Online Estimation of Architectural Vulnerability Factor for Soft Errors. [Citation Graph (, )][DBLP]


  58. Metrics for Architecture-Level Lifetime Reliability Analysis. [Citation Graph (, )][DBLP]


  59. mSWAT: low-cost hardware fault detection and diagnosis for multicore systems. [Citation Graph (, )][DBLP]


  60. A type and effect system for deterministic parallel Java. [Citation Graph (, )][DBLP]


  61. Foundations of the C++ concurrency memory model. [Citation Graph (, )][DBLP]


  62. Memory models: a case for rethinking parallel languages and hardware. [Citation Graph (, )][DBLP]


  63. Memory models: a case for rethinking parallel languages and hardware. [Citation Graph (, )][DBLP]


  64. Memory models: a case for rethinking parallel languages and hardware. [Citation Graph (, )][DBLP]


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