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Author:
Viktor K. Prasanna: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wei-Ming Lin, Viktor K. Prasanna, K. Wojtek Przytula
    Algorithmic Mapping of Neural Network Models onto Parallel SIMD Machines. [Citation Graph (1, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:12, pp:1390-1401 [Journal]
  2. Michael Penner, Viktor K. Prasanna
    Cache-Friendly Implementations of Transitive Closure. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:185-0 [Conf]
  3. Bo Hong, Viktor K. Prasanna
    Constrained Flow Optimization with Applications to Data Gathering in Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ALGOSENSORS, 2004, pp:187-200 [Conf]
  4. Viktor K. Prasanna
    Algorithm Design and Optimization for Sensor Systems: (Invited Talk). [Citation Graph (0, 0)][DBLP]
    ALGOSENSORS, 2004, pp:1-2 [Conf]
  5. Jongwoo Bae, Viktor K. Prasanna
    Synthesis of VLSI Architectures for Two-Dimensional Discrete Wavelet Transforms. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:174-0 [Conf]
  6. Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson
    An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:323-330 [Conf]
  7. Sumit Mohanty, Seonil Choi, Ju-wook Jang, Viktor K. Prasanna
    A Model-Based Methodology for Application Specific Energy Efficient Data Path Design Using FPGAs. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:76-87 [Conf]
  8. Amol Bakshi, Jingzhao Ou, Viktor K. Prasanna
    Towards automatic synthesis of a class of application-specific sensor networks. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:50-58 [Conf]
  9. Sumit Mohanty, Viktor K. Prasanna
    A hierarchical approach for energy efficient application design using heterogeneous embedded systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:243-254 [Conf]
  10. Ramakrishna Soma, Amol Bakshi, Viktor K. Prasanna
    A Semantic Framework for Integrated Asset Management in Smart Oilfields. [Citation Graph (0, 0)][DBLP]
    CCGRID, 2007, pp:119-126 [Conf]
  11. Andreas Dandalis, Viktor K. Prasanna, José D. P. Rolim
    A Comparative Study of Performance of AES Final Candidates Using FPGAs. [Citation Graph (0, 0)][DBLP]
    CHES, 2000, pp:125-140 [Conf]
  12. Bo Hong, Viktor K. Prasanna
    Performance Optimization of a De-centralized Task Allocation Protocol via Bandwidth and Buffer Management. [Citation Graph (0, 0)][DBLP]
    CLADE, 2004, pp:108- [Conf]
  13. Amol Bakshi, Animesh Pathak, Viktor K. Prasanna
    System-level Support for Macroprogramming of Networked Sensing Applications. [Citation Graph (0, 0)][DBLP]
    PSC, 2005, pp:3-11 [Conf]
  14. Viktor K. Prasanna
    High Performance Computing using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ENC, 2005, pp:- [Conf]
  15. Jingzhao Ou, Viktor K. Prasanna
    A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:280-283 [Conf]
  16. Jingzhao Ou, Viktor K. Prasanna
    Rapid Arithmetic Level Simulation Based Energy Estimation for Hardware/Software Co-Design Using FPGAs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:55-61 [Conf]
  17. Viktor K. Prasanna
    Invited Paper: Energy-Efficient Computations on FPGAs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:264-275 [Conf]
  18. Gokul Govindu, Viktor K. Prasanna, Vikash Daga, Sridhar Gangadharpalli, V. Sridhar
    Efficient Floating-point Based Block LU Decomposition on FPGAs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:276-279 [Conf]
  19. Ronald Scrofano, Gokul Govindu, Viktor Pasanna
    A Library of Parameterizable Floating-Point Cores for FPGAs and Their Application to Scientific Computing. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:137-148 [Conf]
  20. Ronald Scrofano, Ju-wook Jang, Viktor K. Prasanna
    Energy-Efficient Discrete Cosine Transform on FPGAs. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:215-221 [Conf]
  21. Ronald Scrofano, Viktor K. Prasanna
    Computing Lennard-Jones Potentials and Forces with Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:284-292 [Conf]
  22. Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna
    Area-Efficient Evaluation of a Class of Arithmetic Expressions Using Deeply Pipelined Floating-Point Cores. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:119-128 [Conf]
  23. Ling Zhuo, Viktor K. Prasanna
    Energy Performance of Floating-Point Matrix Multiplication on FPGAs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:316- [Conf]
  24. Jeoong Sung Park, Hong-Jip Jung, Viktor K. Prasanna
    Efficient FPGA-based Implementations of the MIMO-OFDM Physical Layer. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:153-163 [Conf]
  25. Zachary K. Baker, Viktor K. Prasanna
    Performance Modeling and Interpretive Simulation of PIM Architectures and Applications (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2002, pp:157-161 [Conf]
  26. Yongwha Chung, Viktor K. Prasanna
    An Asynchronous Parallel Algorithm for Symbolic Grouping Operations in Vision. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. II, 1996, pp:123-130 [Conf]
  27. Amol Bakshi, Viktor K. Prasanna
    Structured Communication in Single Hop Sensor Networks. [Citation Graph (0, 0)][DBLP]
    EWSN, 2004, pp:138-153 [Conf]
  28. Zachary K. Baker, Viktor K. Prasanna
    A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:135-144 [Conf]
  29. Zachary K. Baker, Viktor K. Prasanna
    Efficient Hardware Data Mining with the Apriori Algorithm on FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:3-12 [Conf]
  30. Andreas Dandalis, Viktor K. Prasanna
    Mapping Homogeneous Computations onto Dynamically Configurable Coarse-Grained Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:314-0 [Conf]
  31. Andreas Dandalis, Viktor K. Prasanna, José D. P. Rolim
    An Adaptive Cryptographic Engine for IPSec Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:132-144 [Conf]
  32. Kiran Bondalapati, Viktor K. Prasanna
    Dynamic Precision Management for Loop Computations on Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:249-0 [Conf]
  33. Jingzhao Ou, Viktor K. Prasanna
    PyGen: A MATLAB/Simulink Based Tool for Synthesizing Parameterized and Energy Efficient Designs Using FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:47-56 [Conf]
  34. Sumit Mohanty, Jingzhao Ou, Viktor K. Prasanna
    An Estimation and Simulation Framework for Energy Efficient Design using Platform FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:290-291 [Conf]
  35. Sumit Mohanty, Viktor K. Prasanna
    Duty Cycle Aware Application Design using FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:338-339 [Conf]
  36. Jingzhao Ou, Viktor K. Prasanna
    COMA: A COoperative MAnagement Scheme for Energy Efficient Implementation of Real-Time Operating Systems on FPGA Based Soft Processors. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:139-148 [Conf]
  37. Gerald R. Morris, Ling Zhuo, Viktor K. Prasanna
    High-Performance FPGA-Based General Reduction Methods. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:323-324 [Conf]
  38. Jingzhao Ou, Seonil Choi, Viktor K. Prasanna
    Performance Modeling of Reconfigurable SoC Architectures and Energy-Efficient Mapping of a Class of Applications. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:241-250 [Conf]
  39. Ronald Scrofano, Maya Gokhale, Frans Trouw, Viktor K. Prasanna
    Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:23-34 [Conf]
  40. Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson
    A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:3-12 [Conf]
  41. Zachary K. Baker, Viktor K. Prasanna
    An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:67-75 [Conf]
  42. Seonil Choi, Ronald Scrofano, Viktor K. Prasanna, Ju-wook Jang
    Energy-efficient signal processing using FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:225-234 [Conf]
  43. Zachary K. Baker, Viktor K. Prasanna
    Time and area efficient pattern matching on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:223-232 [Conf]
  44. Andreas Dandalis, Viktor K. Prasanna
    Configuration compression for FPGA-based embedded systems. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:173-182 [Conf]
  45. Ronald Scrofano, Viktor K. Prasanna
    A Performance model for accelerating scientific applications on reconfigurable computers. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:234- [Conf]
  46. Reetinder P. S. Sidhu, Alessandro Mei, Viktor K. Prasanna
    String Natching on Nulticontext FPGAs Using Self-Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:217-226 [Conf]
  47. Ling Zhuo, Viktor K. Prasanna
    Sparse Matrix-Vector multiplication on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:63-74 [Conf]
  48. Jingzhao Ou, Viktor K. Prasanna
    A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:729-739 [Conf]
  49. Kiran Bondalapati, Viktor K. Prasanna
    Mapping Loops onto Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:268-277 [Conf]
  50. Kiran Bondalapati, Viktor K. Prasanna
    DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:31-40 [Conf]
  51. Zachary K. Baker, Viktor K. Prasanna
    Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:311-321 [Conf]
  52. Seonil Choi, Viktor K. Prasanna
    Time and Energy Efficient Matrix Factorization Using FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:507-519 [Conf]
  53. Andreas Dandalis, Viktor K. Prasanna
    Fast parallel implementation of DFT using configurable devices. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:314-323 [Conf]
  54. Andreas Dandalis, Viktor K. Prasanna
    Space-efficient Mapping of 2D-DCT onto Dynamically Configurable Coarse-Grained Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:471-475 [Conf]
  55. Andreas Dandalis, Viktor K. Prasanna, Bharani Thiruvengadam
    Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:315-325 [Conf]
  56. Ju-wook Jang, Seonil Choi, Viktor K. Prasanna
    Energy-Efficient Matrix Multiplication on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:534-544 [Conf]
  57. Sumit Mohanty, Viktor K. Prasanna
    An Algorithm Designer's Workbench for Platform FPGA's. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:41-50 [Conf]
  58. Sumit Mohanty, Viktor K. Prasanna
    A Framework for Energy Efficient Design of Multi-rate Applications Using Hybrid Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:658-668 [Conf]
  59. Reetinder P. S. Sidhu, Alessandro Mei, Viktor K. Prasanna
    Genetic Programming Using Self-Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:301-312 [Conf]
  60. Reetinder P. S. Sidhu, Viktor K. Prasanna
    Efficient Metacomputation Using Self-Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:698-709 [Conf]
  61. Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro Mei, Viktor K. Prasanna
    A Self-Reconfigurable Gate Array Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:106-120 [Conf]
  62. Ammar H. Alhusaini, Viktor K. Prasanna, Cauligi S. Raghavendra
    A Framework for Mapping with Resource Co-Allocation in Heterogeneous Computing Systems. [Citation Graph (0, 0)][DBLP]
    Heterogeneous Computing Workshop, 2000, pp:273-286 [Conf]
  63. Ammar H. Alhusaini, Viktor K. Prasanna, Cauligi S. Raghavendra
    A Unified Resource Scheduling Framework for Heterogeneous Computing Environments. [Citation Graph (0, 0)][DBLP]
    Heterogeneous Computing Workshop, 1999, pp:156-0 [Conf]
  64. Debra A. Hensgen, Taylor Kidd, David St. John, Matthew C. Schnaidt, Howard Jay Siegel, Tracy D. Braun, Muthucumaru Maheswaran, Shoukat Ali, Jong-Kook Kim, Cynthia E. Irvine, Timothy E. Levin, Richard F. Freund, Matt Kussow, Michael W. Godfrey, Alpay Duman, Paul Carff, Shirley Kidd, Viktor K. Prasanna, Prashanth B. Bhat, Ammar H. Alhusaini
    An Overview of MSHN: The Management System for Heterogeneous Networks. [Citation Graph (0, 0)][DBLP]
    Heterogeneous Computing Workshop, 1999, pp:184-198 [Conf]
  65. Ashfaq A. Khokhar, Viktor K. Prasanna, Cho-Li Wang
    Scalable Data Parallel Implementations of Object Recognition on Connection Machine CM-. [Citation Graph (0, 0)][DBLP]
    HICSS (2), 1994, pp:130-139 [Conf]
  66. Prashanth B. Bhat, Viktor K. Prasanna, Cauligi S. Raghavendra
    Adaptive Communication Algorithms for Distributed Heterogeneous Systems. [Citation Graph (0, 0)][DBLP]
    HPDC, 1998, pp:310-0 [Conf]
  67. Prashanth B. Bhat, Cauligi S. Raghavendra, Viktor K. Prasanna
    Efficient Collective Communication in Distributed Heterogeneous Systems. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1999, pp:15-24 [Conf]
  68. Salim Hariri, Cauligi S. Raghavendra, Viktor K. Prasanna
    Reliability Analysis in Distributed Systems. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1986, pp:564-571 [Conf]
  69. W. H. Liu, Cho-Li Wang, Viktor K. Prasanna
    Portable Message Passing Algorithms for Irregular All-to-all Communication. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1996, pp:428-435 [Conf]
  70. Amol Bakshi, Viktor K. Prasanna
    Energy-Efficient Communication in Multi-Channel Single-Hop Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ICPADS, 2004, pp:403-410 [Conf]
  71. Seonil Choi, Viktor K. Prasanna, Yongwha Chung
    Configurable Hardware for Symbolic Search Operations. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1997, pp:122-131 [Conf]
  72. Bo Hong, Viktor K. Prasanna
    Adaptive Matrix Multiplication in Heterogeneous Environments. [Citation Graph (0, 0)][DBLP]
    ICPADS, 2002, pp:129-0 [Conf]
  73. Vasanth Krishna Namasivayam, Viktor K. Prasanna
    Scalable Parallel Implementation of Exact Inference in Bayesian Networks. [Citation Graph (0, 0)][DBLP]
    ICPADS (1), 2006, pp:143-150 [Conf]
  74. Mitali Singh, Viktor K. Prasanna
    Energy-Efficient and Fault-Tolerant Resolution of Topographic Queries in Networked Sensor Systems. [Citation Graph (0, 0)][DBLP]
    ICPADS (1), 2006, pp:271-280 [Conf]
  75. Yang Yu, Viktor K. Prasanna
    Power-Aware Resource Allocation for Independent Tasks in Heterogeneous Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ICPADS, 2002, pp:341-348 [Conf]
  76. Ling Zhuo, Viktor K. Prasanna
    Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    ICPADS (1), 2006, pp:87-95 [Conf]
  77. Jongwoo Bae, Viktor K. Prasanna
    A General Framework for Synthesis of Data Format Converters. [Citation Graph (0, 0)][DBLP]
    ICPP, 1994, pp:197-200 [Conf]
  78. Hussein M. Alnuweiri, Viktor K. Prasanna
    Fast Image Labeling using Local Operators On Mesh-Connected Computers. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1989, pp:32-39 [Conf]
  79. Hussein M. Alnuweiri, Viktor K. Prasanna
    Optimal Multipass Self-Routing Algorithms for Clos-Type Multistage Networks. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1992, pp:118-122 [Conf]
  80. Amol Bakshi, Viktor K. Prasanna
    Algorithm Design and Synthesis for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ICPP, 2004, pp:423-430 [Conf]
  81. Bo Hong, Viktor K. Prasanna
    Bandwidth-Aware Resource Allocation for Heterogeneous Computing Systems to Maximize Throughput. [Citation Graph (0, 0)][DBLP]
    ICPP, 2003, pp:539-546 [Conf]
  82. Ju-wook Jang, Viktor K. Prasanna
    Efficient Parallel Algorithms for Some Geometric Problems on Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1992, pp:127-130 [Conf]
  83. Kichul Kim, Viktor K. Prasanna
    An Efficient Mapping of Directed Graph Based Computations onto SIMD Hypercube Arrays and Applications. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1990, pp:296-297 [Conf]
  84. Kichul Kim, Viktor K. Prasanna
    An Iterative Sparse Linear System Solver on Star Graphs. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1991, pp:9-16 [Conf]
  85. Viktor K. Prasanna, Venkatesh Krishnan
    Efficient Image Template Matching on Hypercube SIMD Arrays. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:765-771 [Conf]
  86. Viktor K. Prasanna, Sarma Sastry
    A General Purpose VLSI Array for Efficient Signal and Image Processsing. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:917-920 [Conf]
  87. Viktor K. Prasanna, Yu-Chen Tsai
    Mapping Two Dimensional Systolic Arrays to One Dimensional Arrays and Applications. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:39-46 [Conf]
  88. Viktor K. Prasanna, Mary Mehrnoosh Eshaghian
    Parallel Geometric Algorithms for Digitized Pictures on Mesh of Trees. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:270-273 [Conf]
  89. Young Won Lim, Neungsoo Park, Viktor K. Prasanna
    Efficient Algorithms for Multi-dimensional Block-Cyclic Redistribution of Arrays. [Citation Graph (0, 0)][DBLP]
    ICPP, 1997, pp:234-241 [Conf]
  90. Russ Miller, Viktor K. Prasanna, Dionisios I. Reisis, Quentin F. Stout
    Data Movement Operations and Applications on Reconfigurable VLSI Arrays. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:205-208 [Conf]
  91. Neungsoo Park, Bo Hong, Viktor K. Prasanna
    Analysis of Memory Hierarchy Performance of Block Data Layout. [Citation Graph (0, 0)][DBLP]
    ICPP, 2002, pp:35-0 [Conf]
  92. Heonchul Park, Viktor K. Prasanna
    A Class of Optimal VLSI Architectures for Computing Discrete Fourier Transform. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1992, pp:61-68 [Conf]
  93. Heonchul Park, Viktor K. Prasanna, Ju-wook Jang
    Fast Arithmetic on Reconfigurable Meshes. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:236-243 [Conf]
  94. Viktor K. Prasanna, Anil S. Rao
    Parallel Orientation of Polygonal Parts. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1992, pp:115-122 [Conf]
  95. Dionisios I. Reisis, Viktor K. Prasanna
    Parallel Image Processing On Enhanced Arrays. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:909-912 [Conf]
  96. Jinwoo Suh, Viktor K. Prasanna
    An Efficient Algorithm for Large-Scale Matrix Transposition. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:327-334 [Conf]
  97. Ping-Sheng Tseng, Kai Hwang, Viktor K. Prasanna
    A VLSI-Based Multiprocessor Architecture for Implementing Parallel Algorithms. [Citation Graph (0, 0)][DBLP]
    ICPP, 1985, pp:657-664 [Conf]
  98. Ling Zhuo, Viktor K. Prasanna
    Design Tradeoffs for BLAS Operations on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ICPP, 2005, pp:78-86 [Conf]
  99. Dionisios I. Reisis, Viktor K. Prasanna
    VLSI Arrays with Reconfigurable Buses. [Citation Graph (0, 0)][DBLP]
    ICS, 1987, pp:732-743 [Conf]
  100. Ramakrishna Soma, Amol Bakshi, Viktor K. Prasanna, Will Da Sie
    A Model-Based Framework for Developing and Deploying Data Aggregation Services. [Citation Graph (0, 0)][DBLP]
    ICSOC, 2006, pp:227-239 [Conf]
  101. Mitali Singh, Viktor K. Prasanna, José D. P. Rolim, Cauligi S. Raghavendra
    Collaborative and Distributed Computation in Mesh-Like Wireless Sensor Arrays. [Citation Graph (0, 0)][DBLP]
    PWC, 2003, pp:1-11 [Conf]
  102. Yang Yu, Bhaskar Krishnamachari, Viktor K. Prasanna
    Energy-Latency Tradeoffs for Data Gathering in Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2004, pp:- [Conf]
  103. Ammar H. Alhusaini, Cauligi S. Raghavendra, Viktor K. Prasanna
    Run-Time Adaptation for Grid Environments. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:87- [Conf]
  104. Shoukat Ali, Jong-Kook Kim, Yang Yu, Shriram B. Gundala, Sethavidh Gertphol, Howard Jay Siegel, Anthony A. Maciejewski, Viktor K. Prasanna
    Utilization-Based Heuristics for Statically Mapping Real-Time Applications onto the HiPer-D Heterogeneous Computing System. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  105. Kiran Bondalapati, Viktor K. Prasanna
    Loop Pipelining and Optimization for Run Time Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:906-915 [Conf]
  106. Yongwha Chung, K. Park, W. Hahn, Neungsoo Park, Viktor K. Prasanna
    Performance of On-Chip Multiprocessors for Vision Tasks. [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:242-249 [Conf]
  107. Andreas Dandalis, Alessandro Mei, Viktor K. Prasanna
    Domain Specific Mapping for Solving Graph Problems on Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:652-660 [Conf]
  108. Hossam A. ElGindy, Viktor K. Prasanna, Hartmut Schmeck, Oliver Diessel
    Configurable Architectures Workshop (RAW 2000). [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:870-872 [Conf]
  109. Sethavidh Gertphol, Viktor K. Prasanna
    MIP Formulation for Robust Resource Allocation in Dynamic Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:117- [Conf]
  110. Sethavidh Gertphol, Viktor K. Prasanna
    Iterative Integer Programming Formuation for Robust Resource Allocation in Dynamic Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  111. Sethavidh Gertphol, Yang Yu, Ammar H. Alhusaini, Viktor K. Prasanna
    An integer programming approach for static mapping onto heterogeneous real-time systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:95- [Conf]
  112. Sethavidh Gertphol, Yang Yu, Shriram B. Gundala, Viktor K. Prasanna, Shoukat Ali, Jong-Kook Kim, Anthony A. Maciejewski, Howard Jay Siegel
    A Metric and Mixed-Integer-Programming-Based Approach for Resource Allocation in Dynamic Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  113. Gokul Govindu, Seonil Choi, Viktor K. Prasanna, Vikash Daga, Sridhar Gangadharpalli, V. Sridhar
    A High-Performance and Energy-Efficient Architecture for Floating-Point Based LU Decomposition on FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  114. Gokul Govindu, Ling Zhuo, Seonil Choi, Viktor K. Prasanna
    Analysis of High-Performance Floating-Point Arithmetic on FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  115. Bo Hong, Viktor K. Prasanna
    Distributed Adaptive Task Allocation in Heterogeneous Computing Environments to Maximize Throughput. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  116. Ju-wook Jang, Viktor K. Prasanna
    An Optimal Sorting Algorithm on Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:130-137 [Conf]
  117. Jong-Kook Kim, Taylor Kidd, Howard Jay Siegel, Cynthia E. Irvine, Timothy E. Levin, Debra A. Hensgen, David St. John, Viktor K. Prasanna, Richard F. Freund, N. Wayne Porter
    Collective Value of QoS: A Performance Measure Framework for Distributed Heterogeneous Networks. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:84- [Conf]
  118. Myungho Lee, Wenheng Liu, Viktor K. Prasanna
    A Mapping Methodology for Designing Software Task Pipelines for Embedded Signal Processing. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1998, pp:937-944 [Conf]
  119. Jingzhao Ou, Viktor K. Prasanna
    MATLAB/Simulink Based Hardware/Software Co-Simulation for Designing Using FPGA Configured Soft Processors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  120. Neungsoo Park, Dongsoo Kang, Kiran Bondalapati, Viktor K. Prasanna
    Dynamic Data Layouts for Cache-Conscious Factorization of DFT. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:693-702 [Conf]
  121. Joon-Sang Park, Michael Penner, Viktor K. Prasanna
    Optimizing Graph Algorithms for Improved Cache Performance. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  122. Viktor K. Prasanna, Cauligi S. Raghavendra
    Heterogeneous Computing Workshop (HCW 2000). [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:1301-1306 [Conf]
  123. Mitali Singh, Viktor K. Prasanna
    A Hierarchical Model for Distributed Collaborative Computation in Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:166- [Conf]
  124. Yang Yu, Viktor K. Prasanna, Bo Hong
    Communication Models for Algorithm Design in Networked Sensor Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  125. Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
    Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  126. Ling Zhuo, Viktor K. Prasanna
    Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  127. Kwatra Kwatra, Viktor K. Prasanna, Mitali Singh
    Accelerating DTI tractography using FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  128. Hong-Jip Jung, Zachary K. Baker, Viktor K. Prasanna
    Performance of FPGA implementation of bit-split architecture for intrusion detection systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  129. Akis Spyropoulos, Cauligi S. Raghavendra, Viktor K. Prasanna
    A Distributed Algorithm for Waking-up in Heterogeneous Sensor Networks. [Citation Graph (0, 0)][DBLP]
    IPSN, 2003, pp:609-624 [Conf]
  130. Cong Zhang, Amol Bakshi, Viktor K. Prasanna, Will Da Sie
    Towards a model-based application integration framework for smart oilfields. [Citation Graph (0, 0)][DBLP]
    IRI, 2006, pp:545-550 [Conf]
  131. Cong Zhang, Viktor K. Prasanna, Abdollah Orangi, Will Da Sie, Aditya Kwatra
    Modeling methodology for application development in petroleum industry. [Citation Graph (0, 0)][DBLP]
    IRI, 2005, pp:445-451 [Conf]
  132. Kichul Kim, Viktor K. Prasanna
    Perfect Latin Squares and Parallel Array Access. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:372-379 [Conf]
  133. Viktor K. Prasanna, Cauligi S. Raghavendra
    Array Processor with Multiple Broadcasting. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:2-10 [Conf]
  134. Caimu Tang, Cauligi S. Raghavendra, Viktor K. Prasanna
    Energy Efficient Adaptation of Multicast Protocols in Power Controlled Wireless Ad Hoc Networks. [Citation Graph (0, 0)][DBLP]
    ISPAN, 2002, pp:91-0 [Conf]
  135. Amol Bakshi, Viktor K. Prasanna
    Programming Paradigms for Networked Sensing: A Distributed Systems' Perspective. [Citation Graph (0, 0)][DBLP]
    IWDC, 2005, pp:451-462 [Conf]
  136. Sumit Mohanty, Viktor K. Prasanna, Sandeep Neema, James R. Davis
    Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation. [Citation Graph (0, 0)][DBLP]
    LCTES-SCOPES, 2002, pp:18-27 [Conf]
  137. Amol Bakshi, Viktor K. Prasanna, Ákos Lédeczi
    MILAN: A Model Based Integrated Simulation Framework for Desgin of Embedded Suystems. [Citation Graph (0, 0)][DBLP]
    LCTES/OM, 2001, pp:82-87 [Conf]
  138. Yang Yu, Viktor K. Prasanna
    Energy-balanced task allocation for collaborative processing in networked embedded systems. [Citation Graph (0, 0)][DBLP]
    LCTES, 2003, pp:265-274 [Conf]
  139. Jinwoo Suh, Viktor K. Prasanna
    Portable Implementation of Real-Time Signal Processing Benchmarks on HPC Platforms. [Citation Graph (0, 0)][DBLP]
    PARA, 1998, pp:527-536 [Conf]
  140. Shoukat Ali, Jong-Kook Kim, Howard Jay Siegel, Anthony A. Maciejewski, Yang Yu, Shriram B. Gundala, Sethavidh Gertphol, Viktor K. Prasanna
    Greedy Heuristics for Resource Allocation in Dynamic Distributed Real-Time Heterogeneous Computing Systems. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2002, pp:519-530 [Conf]
  141. Kiran Bondalapati, Viktor K. Prasanna
    Hardware Object Selection for Mapping Loops onto Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:1104-1110 [Conf]
  142. Mitali Singh, Viktor K. Prasanna
    Energy-Optimal and Energy-Balanced Sorting in a Single-Hop Wireless Sensor Network. [Citation Graph (0, 0)][DBLP]
    PerCom, 2003, pp:50-59 [Conf]
  143. Mitali Singh, Viktor K. Prasanna
    Supporting Topographic Queries in a Class of Networked Sensor Systems. [Citation Graph (0, 0)][DBLP]
    PerCom Workshops, 2005, pp:362-368 [Conf]
  144. Afshin Daghi, Viktor K. Prasanna, Ali Safavi
    An Efficient Fixed Size Array for Solving Large Scale Toeplitz Systems-Abstract. [Citation Graph (0, 0)][DBLP]
    PPSC, 1987, pp:19- [Conf]
  145. Prashanth B. Bhat, Young Won Lim, Viktor K. Prasanna
    Issues in using heterogeneous HPC systems for embedded real time signal processing applications. [Citation Graph (0, 0)][DBLP]
    RTCSA, 1995, pp:134-141 [Conf]
  146. Ling Zhuo, Viktor K. Prasanna
    High Performance Linear Algebra Operations on Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    SC, 2005, pp:2- [Conf]
  147. Ronald Scrofano, Viktor K. Prasanna
    Molecular dynamics - Preliminary investigation of advanced electrostatics in molecular dynamics on reconfigurable computers. [Citation Graph (0, 0)][DBLP]
    SC, 2006, pp:90- [Conf]
  148. Hussein M. Alnuweiri, Viktor K. Prasanna
    Parallel Convexity Algorithms for Digitized Images on a Linear Array of Processors. [Citation Graph (0, 0)][DBLP]
    SIGAL International Symposium on Algorithms, 1990, pp:397-406 [Conf]
  149. Ju-wook Jang, Heonchul Park, Viktor K. Prasanna
    An Optimal Multiplication Algorithm for Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    SPDP, 1992, pp:384-391 [Conf]
  150. Cho-Chin Lin, Viktor K. Prasanna
    A Tight Bound on the Diameter of One-Dimensional PEC Networks. [Citation Graph (0, 0)][DBLP]
    SPDP, 1992, pp:368-375 [Conf]
  151. Heonchul Park, Viktor K. Prasanna
    A Fast Algorithm for Performing Vector Quantization and its VLSI Implementation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:91-94 [Conf]
  152. Claude Tadonki, Mitali Singh, José D. P. Rolim, Viktor K. Prasanna
    Combinatorial Techniques for Memory Power State Scheduling in Energy-Constrained Systems. [Citation Graph (0, 0)][DBLP]
    WAOA, 2003, pp:265-268 [Conf]
  153. Mitali Singh, Viktor K. Prasanna
    Algorithmic Techniques for Memory Energy Reduction. [Citation Graph (0, 0)][DBLP]
    WEA, 2003, pp:237-252 [Conf]
  154. Zachary K. Baker, Viktor K. Prasanna
    High-throughput linked-pattern matching for intrusion detection systems. [Citation Graph (0, 0)][DBLP]
    ANCS, 2005, pp:193-202 [Conf]
  155. Hussein M. Alnuweiri, Viktor K. Prasanna
    Processor-Time Optimal Parallel Algorithms for Digitized Images on Mesh-Connected Processor Arrays. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1991, v:6, n:5, pp:698-733 [Journal]
  156. Myungho Lee, Wenheng Liu, Viktor K. Prasanna
    Parallel Implementation of a Class of Adaptive Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 2001, v:30, n:4, pp:645-684 [Journal]
  157. Young Won Lim, Prashanth B. Bhat, Viktor K. Prasanna
    Efficient Algorithms for Block-Cyclic Redistribution of Arrays. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1999, v:24, n:3-4, pp:298-330 [Journal]
  158. Prashanth B. Bhat, Viktor K. Prasanna, Cauligi S. Raghavendra
    Block-cyclic redistribution over heterogeneous networks. [Citation Graph (0, 0)][DBLP]
    Cluster Computing, 2000, v:3, n:1, pp:25-34 [Journal]
  159. Jong-Kook Kim, Debra A. Hensgen, Taylor Kidd, Howard Jay Siegel, David St. John, Cynthia E. Irvine, Timothy E. Levin, N. Wayne Porter, Viktor K. Prasanna, Richard F. Freund
    A flexible multi-dimensional QoS performance measure framework for distributed heterogeneous systems. [Citation Graph (0, 0)][DBLP]
    Cluster Computing, 2006, v:9, n:3, pp:281-296 [Journal]
  160. Ashfaq A. Khokhar, Viktor K. Prasanna, Muhammad E. Shaaban, Cho-Li Wang
    Heterogeneous Computing: Challenges and Opportunities. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1993, v:26, n:6, pp:18-27 [Journal]
  161. William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg
    Seeking Solutions in Configurable Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:38-43 [Journal]
  162. Milind Mahajan, Viktor K. Prasanna
    Efficient parallel implementation of RETE pattern matching. [Citation Graph (0, 0)][DBLP]
    Comput. Syst. Sci. Eng., 1990, v:5, n:3, pp:187-192 [Journal]
  163. Wei-Ming Lin, Viktor K. Prasanna
    Efficient Histogramming on Hypercube SIMD Machines. [Citation Graph (0, 0)][DBLP]
    Computer Vision, Graphics, and Image Processing, 1990, v:49, n:1, pp:104-120 [Journal]
  164. Katherine Heinrich, Kichul Kim, Viktor K. Prasanna
    Perfect Latin Squares. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 1992, v:37, n:, pp:281-286 [Journal]
  165. Hussein M. Alnuweiri, Viktor K. Prasanna
    Optimal Geometric Algorithms for Digitized Images on Fixed-Size Linear Arrays and Scan-Line Arrays. [Citation Graph (0, 0)][DBLP]
    Distributed Computing, 1991, v:5, n:, pp:55-65 [Journal]
  166. Mitali Singh, Viktor K. Prasanna
    A Hierarchical Model For Distributed Collaborative Computation In Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 2004, v:15, n:3, pp:485-506 [Journal]
  167. Heonchul Park, Hyoung Joong Kim, Viktor K. Prasanna
    An O(1) Time Optimal Algorithm for Multiplying Matrices on Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1993, v:47, n:2, pp:109-113 [Journal]
  168. Joseph JáJá, Viktor K. Prasanna
    Information Transfer in Distributed Computing with Applications to VLSI. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1984, v:31, n:1, pp:150-162 [Journal]
  169. Michael Penner, Viktor K. Prasanna
    Cache-Friendly implementations of transitive closure. [Citation Graph (0, 0)][DBLP]
    ACM Journal of Experimental Algorithms, 2006, v:11, n:, pp:- [Journal]
  170. Yang Yu, Viktor K. Prasanna
    Resource Allocation for Independent Real-Time Tasks in Heterogeneous Systems for Energy Minimization. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2003, v:19, n:3, pp:433-449 [Journal]
  171. Hussein M. Alnuweiri, Viktor K. Prasanna
    Efficient Parallel Computation on the Reduced Mesh of Tress Organization. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1994, v:20, n:2, pp:121-135 [Journal]
  172. Prashanth B. Bhat, Viktor K. Prasanna, Cauligi S. Raghavendra
    Adaptive Communication Algorithms for Distributed Heterogeneous Systems. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1999, v:59, n:2, pp:252-279 [Journal]
  173. Prashanth B. Bhat, Cauligi S. Raghavendra, Viktor K. Prasanna
    Efficient collective communication in distributed heterogeneous systems. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2003, v:63, n:3, pp:251-263 [Journal]
  174. Yongwha Chung, Cho-Li Wang, Viktor K. Prasanna
    Parallel Algorithms for Perceptual Grouping on Distributed Memory Machines. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1998, v:50, n:1/2, pp:123-143 [Journal]
  175. Ju-wook Jang, Viktor K. Prasanna
    An Optimal Sorting Algorithm on Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:25, n:1, pp:31-41 [Journal]
  176. Viktor K. Prasanna, Cauligi S. Raghavendra
    Array Processor with Multiple Broadcasting. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1987, v:4, n:2, pp:173-190 [Journal]
  177. Viktor K. Prasanna, Yu-Chen Tsai
    Designing Linear Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1989, v:7, n:3, pp:441-463 [Journal]
  178. Cho-Chin Lin, Viktor K. Prasanna
    Bounds on the Diameter of One-Dimensional PEC Networks. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:29, n:1, pp:1-16 [Journal]
  179. Wenheng Liu, Cho-Li Wang, Viktor K. Prasanna
    Portable and Scalable Algorithm for Irregular All-to-All Communication. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2002, v:62, n:10, pp:1493-1526 [Journal]
  180. Viktor K. Prasanna
    Special Issue on Massively Parallel Computation. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1991, v:13, n:2, pp:123- [Journal]
  181. Cho-Li Wang, Viktor K. Prasanna, Hyoung Joong Kim, Ashfaq A. Khokhar
    Scalable Data Parallel Implementations of Object Recognition Using Geometric Hashing. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1994, v:21, n:1, pp:96-109 [Journal]
  182. Bo Hong, Viktor K. Prasanna
    Maximum lifetime data sensing and extraction in energy constrained networked sensor systems. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2006, v:66, n:4, pp:566-577 [Journal]
  183. Sethavidh Gertphol, Viktor K. Prasanna
    MIP formulation for robust resource allocation in dynamic real-time systems. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2005, v:77, n:1, pp:55-65 [Journal]
  184. Yang Yu, Viktor K. Prasanna
    Energy-Balanced Task Allocation for Collaborative Processing in Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    MONET, 2005, v:10, n:1-2, pp:115-131 [Journal]
  185. Bharadwaj Veeravalli, Chaoyang Chen, Viktor K. Prasanna
    Fault-tolerant analysis for multiple servers movie retrieval strategy for distributed multimedia applications. [Citation Graph (0, 0)][DBLP]
    Multimedia Tools Appl., 2007, v:32, n:1, pp:1-27 [Journal]
  186. Yang Yu, Bhaskar Krishnamachari, Viktor K. Prasanna
    Issues in Designing Middleware for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Network, 2004, v:18, n:1, pp:15-21 [Journal]
  187. Hussein M. Alnuweiri, Viktor K. Prasanna
    Fast Image Labeling Using Local Operators on Mesh-Connected Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1991, v:13, n:2, pp:202-207 [Journal]
  188. Hussein M. Alnuweiri, Viktor K. Prasanna
    Parallel Architectures and Algorithms for Image Component Labeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1992, v:14, n:10, pp:1014-1034 [Journal]
  189. Yongwha Chung, Viktor K. Prasanna
    Parallelizing Image Feature Extraction on Coarse-Grain Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1998, v:20, n:12, pp:1389-1394 [Journal]
  190. Ju-wook Jang, Heonchul Park, Viktor K. Prasanna
    A Fast Algorithm for Computing a Histogram on Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1995, v:17, n:2, pp:97-106 [Journal]
  191. Viktor K. Prasanna, Venkatesh Krishnan
    Efficient Parallel Algorithms for Image Template Matching on Hypercube SIMD Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1989, v:11, n:6, pp:665-669 [Journal]
  192. Viktor K. Prasanna, Dionisios I. Reisis
    Image Computations on Meshes with Multiple Broadcast. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1989, v:11, n:11, pp:1194-1202 [Journal]
  193. Hussein M. Alnuweiri, Viktor K. Prasanna
    An efficient VLSI architecture with applications to geometric problems. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1989, v:12, n:1, pp:71-93 [Journal]
  194. Manavendra Misra, David Nassimi, Viktor K. Prasanna
    Efficient VLSI Implementation of Iterative Solutions to Sparse Linear Systems. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1993, v:19, n:5, pp:525-544 [Journal]
  195. Joseph JáJá, Viktor K. Prasanna, Janos Simon
    Information Transfer under Different Sets of Protocols. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1984, v:13, n:4, pp:840-849 [Journal]
  196. Hussein M. Alnuweiri, Viktor K. Prasanna
    Optimal VLSI Sorting with Reduced Number of Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:1, pp:105-110 [Journal]
  197. Viktor K. Prasanna, Yu-Chen Tsai
    On Mapping Algorithms to Linear and Fault-Tolerant Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:3, pp:470-478 [Journal]
  198. Viktor K. Prasanna, Yu-Chen Tsai
    On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:6, pp:770-774 [Journal]
  199. Wei-Ming Lin, Viktor K. Prasanna
    A Note on the Linear Transformation Method for Systolic Array Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:3, pp:393-399 [Journal]
  200. Russ Miller, Viktor K. Prasanna, Dionisios I. Reisis, Quentin F. Stout
    Parallel Computations on Reconfigurable Meshes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:6, pp:678-692 [Journal]
  201. Viktor K. Prasanna
    Editor's Note. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:1, pp:3- [Journal]
  202. Viktor K. Prasanna
    Editor's Note. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:3, pp:257-259 [Journal]
  203. Viktor K. Prasanna
    Editor's Note. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:7, pp:833-834 [Journal]
  204. Viktor K. Prasanna
    Editor's Note. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:11, pp:1377-1378 [Journal]
  205. Viktor K. Prasanna
    Editor's Note. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:7, pp:785-787 [Journal]
  206. Viktor K. Prasanna
    Editor's Note. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:3, pp:241-242 [Journal]
  207. Viktor K. Prasanna
    Introducting the New Editor-in-Chief of the IEEE Transactions on Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:12, pp:1489-1490 [Journal]
  208. Viktor K. Prasanna, Fabrizio Lombardi
    Editor's Note. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:2, pp:97-0 [Journal]
  209. Viktor K. Prasanna, Fabrizio Lombardi
    Editors' Note. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:1, pp:1- [Journal]
  210. Cauligi S. Raghavendra, Viktor K. Prasanna
    Permutations on Illiac IV-Type Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:7, pp:663-669 [Journal]
  211. Cauligi S. Raghavendra, Viktor K. Prasanna, Salim Hariri
    Reliability Analysis in Distributed Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:3, pp:352-358 [Journal]
  212. Jinwoo Suh, Viktor K. Prasanna
    An Efficient Algorithm for Out-of-Core Matrix Transposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:4, pp:420-438 [Journal]
  213. Zachary K. Baker, Viktor K. Prasanna
    Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Dependable Sec. Comput., 2006, v:3, n:4, pp:289-300 [Journal]
  214. Jingzhao Ou, Viktor K. Prasanna
    Design space exploration using arithmetic-level hardware--software cosimulation for configurable multiprocessor platforms. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:355-382 [Journal]
  215. Seonil Choi, Ju-wook Jang, Sumit Mohanty, Viktor K. Prasanna
    Domain-Specific Modeling for Rapid Energy Estimation of Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2003, v:26, n:3, pp:259-281 [Journal]
  216. Viktor K. Prasanna
    Energy-Efficient Computations on FPGAs. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2005, v:32, n:2, pp:139-162 [Journal]
  217. Andreas Dandalis, Viktor K. Prasanna
    Run-time performance optimization of an FPGA-based deduction engine for SAT solvers. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:547-562 [Journal]
  218. Andreas Dandalis, Viktor K. Prasanna
    An adaptive cryptographic engine for internet protocol security architectures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:3, pp:333-353 [Journal]
  219. Ju-wook Jang, Madhusudan Nigam, Viktor K. Prasanna, Sartaj Sahni
    Constant Time Algorithms for Computational Geometry on the Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:1, pp:1-12 [Journal]
  220. Ju-wook Jang, Heonchul Park, Viktor K. Prasanna
    An Optimal Multiplication Algorithm on Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:5, pp:521-532 [Journal]
  221. Kichul Kim, Viktor K. Prasanna
    Latin Squares for Parallel Array Access. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:4, pp:361-370 [Journal]
  222. Neungsoo Park, Bo Hong, Viktor K. Prasanna
    Tiling, Block Data Layout, and Memory Hierarchy Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:7, pp:640-654 [Journal]
  223. Joon-Sang Park, Michael Penner, Viktor K. Prasanna
    Optimizing Graph Algorithms for Improved Cache Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:9, pp:769-782 [Journal]
  224. Neungsoo Park, Viktor K. Prasanna, Cauligi S. Raghavendra
    Efficient Algorithms for Block-Cyclic Array Redistribution Between Processor Sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1999, v:10, n:12, pp:1217-1240 [Journal]
  225. Ling Zhuo, Viktor K. Prasanna
    Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:4, pp:433-448 [Journal]
  226. Viktor K. Prasanna, Salim Hariri, Cauligi S. Raghavendra
    Distributed Program Reliability Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1986, v:12, n:1, pp:42-50 [Journal]
  227. Zachary K. Baker, Viktor K. Prasanna
    A computationally efficient engine for flexible intrusion detection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1179-1189 [Journal]
  228. Ju-wook Jang, S. B. Choi, Viktor K. Prasanna
    Energy- and time-efficient matrix multiplication on FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1305-1319 [Journal]
  229. Andreas Dandalis, Viktor K. Prasanna
    Configuration compression for FPGA-based embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1394-1398 [Journal]
  230. Ramakrishna Soma, Amol Bakshi, Viktor K. Prasanna
    An Architecture of a Workflow System for Integrated Asset Management in the Smart Oil Field Domain. [Citation Graph (0, 0)][DBLP]
    IEEE SCW, 2007, pp:191-198 [Conf]
  231. Animesh Pathak, Luca Mottola, Amol Bakshi, Viktor K. Prasanna, Gian Pietro Picco
    A Compilation Framework for Macroprogramming Networked Sensors. [Citation Graph (0, 0)][DBLP]
    DCOSS, 2007, pp:189-204 [Conf]
  232. Ling Zhuo, Viktor K. Prasanna
    High-Performance and Parameterized Matrix Factorization on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  233. Zachary K. Baker, Viktor K. Prasanna, Hong-Jip Jung
    Regular Expression Software Deceleration for Intrusion Detection Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-8 [Conf]
  234. Ling Zhuo, Viktor K. Prasanna
    Hardware/Software Co-Design for Matrix Computations on Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-10 [Conf]
  235. David A. Bader, Viktor K. Prasanna
    DOSA: Design Optimizer for Scientific Applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  236. Cong Zhang, Amol Bakshi, Viktor K. Prasanna
    ModelML: a Markup Language for Automatic Model Synthesis. [Citation Graph (0, 0)][DBLP]
    IRI, 2007, pp:317-322 [Conf]
  237. Xiaorong Li, Bharadwaj Veeravalli, Viktor K. Prasanna
    A window-assisted video partitioning strategy for partitioning and caching video streams in distributed multimedia systems. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2007, v:67, n:6, pp:738-754 [Journal]
  238. Sumit Mohanty, Viktor K. Prasanna
    A model-based extensible framework for efficient application design using FPGA. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:2, pp:- [Journal]
  239. Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
    High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:10, pp:1377-1392 [Journal]
  240. Bo Hong, Viktor K. Prasanna
    Adaptive Allocation of Independent Tasks to Maximize Throughput. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:10, pp:1420-1435 [Journal]
  241. Jongwoo Bae, Viktor K. Prasanna
    Synthesis of area-efficient and high-throughput rate data format converters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:697-706 [Journal]
  242. Jingzhao Ou, Viktor K. Prasanna
    Arithmetic-Level Instruction Based Energy Estimation for FPGA based Soft Processors. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:161-171 [Journal]

  243. A Data Partitioning Approach for Parallelizing Rule Based Inferencing for Materialized OWL Knowledge Bases. [Citation Graph (, )][DBLP]


  244. A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification. [Citation Graph (, )][DBLP]


  245. Collaborative scheduling of DAG structured computations on multicore processors. [Citation Graph (, )][DBLP]


  246. Multi-terabit ip lookup using parallel bidirectional pipelines. [Citation Graph (, )][DBLP]


  247. Energy-Efficient Task Mapping for Data-Driven Sensor Network Macroprogramming. [Citation Graph (, )][DBLP]


  248. Scientific Computing using Reconfigurable Hardware. [Citation Graph (, )][DBLP]


  249. Algorithm Design for Reconfigurable Computing Systems. [Citation Graph (, )][DBLP]


  250. Scalable High Throughput and Power Efficient IP-Lookup on FPGA. [Citation Graph (, )][DBLP]


  251. A SRAM-based Architecture for Trie-based IP Lookup Using FPGA. [Citation Graph (, )][DBLP]


  252. Matrix Computations on Heterogeneous Reconfigurable Systems. [Citation Graph (, )][DBLP]


  253. Multi-Core Architecture on FPGA for Large Dictionary String Matching. [Citation Graph (, )][DBLP]


  254. Memory-Efficient Pipelined Architecture for Large-Scale String Matching. [Citation Graph (, )][DBLP]


  255. Large-scale wire-speed packet classification on FPGAs. [Citation Graph (, )][DBLP]


  256. High throughput and large capacity pipelined dynamic search tree on FPGA. [Citation Graph (, )][DBLP]


  257. Memory efficient string matching: a modular approach on FPGAs (abstract only). [Citation Graph (, )][DBLP]


  258. Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA. [Citation Graph (, )][DBLP]


  259. Parallel Inferencing for OWL Knowledge Bases. [Citation Graph (, )][DBLP]


  260. Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup. [Citation Graph (, )][DBLP]


  261. High Performance Dictionary-Based String Matching for Deep Packet Inspection. [Citation Graph (, )][DBLP]


  262. Parallel IP lookup using multiple SRAM-based pipelines. [Citation Graph (, )][DBLP]


  263. DOSA: design optimizer for scientific applications. [Citation Graph (, )][DBLP]


  264. Junction tree decomposition for parallel exact inference. [Citation Graph (, )][DBLP]


  265. Transitive closure on the cell broadband engine: A study on self-scheduling in a multicore processor. [Citation Graph (, )][DBLP]


  266. Towards an integrated modeling and simulation framework for freight transportation in metropolitan areas. [Citation Graph (, )][DBLP]


  267. Workflow instance detection: Toward a knowledge capture methodology for smart oilfields. [Citation Graph (, )][DBLP]


  268. Data component based management of reservoir simulation models. [Citation Graph (, )][DBLP]


  269. An FPGA-Based Floating-Point Jacobi Iterative Solver. [Citation Graph (, )][DBLP]


  270. Provenance Collection in Reservoir Management Workflow Environments. [Citation Graph (, )][DBLP]


  271. Applying Semantic Web Techniques to Reservoir Engineering: Challenges and Experiences from Event Modeling. [Citation Graph (, )][DBLP]


  272. Detecting Dirty Queries during Iterative Development of OWL Based Applications. [Citation Graph (, )][DBLP]


  273. Parallel Evidence Propagation on Multicore Processors. [Citation Graph (, )][DBLP]


  274. Hierarchical Dependency Graphs: Abstraction and Methodology for Mapping Systolic Array Designs to Multicore Processors. [Citation Graph (, )][DBLP]


  275. Parallel Exact Inference. [Citation Graph (, )][DBLP]


  276. Optimizing Matrix Multiplication on Heterogeneous Reconfigurable Systems. [Citation Graph (, )][DBLP]


  277. Expressing Sensor Network Interaction Patterns Using Data-Driven Macroprogramming. [Citation Graph (, )][DBLP]


  278. Node Level Primitives for Parallel Exact Inference. [Citation Graph (, )][DBLP]


  279. Scalable Parallel Implementation of Bayesian Network to Junction Tree Conversion for Exact Inference. [Citation Graph (, )][DBLP]


  280. High-Performance and Area-Efficient Reduction Circuits on FPGAs. [Citation Graph (, )][DBLP]


  281. Parallel exact inference on the cell broadband engine processor. [Citation Graph (, )][DBLP]


  282. Field-split parallel architecture for high performance multi-match packet classification using FPGAs. [Citation Graph (, )][DBLP]


  283. Compact architecture for high-throughput regular expression matching on FPGA. [Citation Graph (, )][DBLP]


  284. Multi-Way Pipelining for Power-Efficient IP Lookup. [Citation Graph (, )][DBLP]


  285. Energy-Efficient Multi-Pipeline Architecture for Terabit Packet Classification. [Citation Graph (, )][DBLP]


  286. Issues in designing a compilation framework for macroprogrammed networked sensor systems. [Citation Graph (, )][DBLP]


  287. Automatic Construction of Large-Scale Regular Expression Matching Engines on FPGA. [Citation Graph (, )][DBLP]


  288. Sparse Matrix Computations on Reconfigurable Hardware. [Citation Graph (, )][DBLP]


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